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/Documentation/devicetree/bindings/regulator/
Dti-abb-regulator.txt25 - ti,tranxdone-status-mask: Mask to the int-register to write-to-clear mask
36 RBB enable efuse Mask: (See Optional properties)
37 FBB enable efuse Mask: (See Optional properties)
38 Vset value efuse Mask: (See Optional properties)
50 - ti,ldovbb-vset-mask - Required if ldo-address is set, mask for LDO override
52 - ti,ldovbb-override-mask - Required if ldo-address is set, mask for LDO
58 RBB enable efuse Mask: Optional if 'efuse-address' register is defined.
60 + efuse maps to RBB mask. Set to 0 to ignore this.
61 FBB enable efuse Mask: Optional if 'efuse-address' register is defined.
63 + efuse maps to FBB mask (valid only if RBB mask does not match)
[all …]
/Documentation/devicetree/bindings/sound/
Dtdm-slot.txt8 dai-tdm-slot-tx-mask : Transmit direction slot mask, optional
9 dai-tdm-slot-rx-mask : Receive direction slot mask, optional
14 dai-tdm-slot-tx-mask = <0 1>;
15 dai-tdm-slot-rx-mask = <1 0>;
29 does not do anything, if either mask is set non zero value.
Damlogic,axg-sound-card.yaml53 accommodate the largest mask provided.
73 "^dai-tdm-slot-(t|r)x-mask-[0-3]$":
79 When omitted, mask is assumed to have to no slots. A valid
81 mask should be provided with an enabled slot.
97 "^dai-tdm-slot-(t|r)x-mask$":
152 dai-tdm-slot-tx-mask-2 = <1 1>;
153 dai-tdm-slot-tx-mask-3 = <1 1>;
154 dai-tdm-slot-rx-mask-1 = <1 1>;
/Documentation/devicetree/bindings/hwmon/
Dmax6697.txt30 - alert-mask
31 Alert bit mask. Alert disabled for bits set.
34 - over-temperature-mask
35 Over-temperature bit mask. Over-temperature reporting disabled for
44 specified as boolean, otherwise as per bit mask specified.
49 For MAX6581 only. Two values; first is bit mask, second is ideality
62 alert-mask = <0x72>;
63 over-temperature-mask = <0x7f>;
/Documentation/devicetree/bindings/mtd/
Ddavinci-nand.txt27 - ti,davinci-mask-ale: mask for ALE. Needed for executing address
33 - ti,davinci-mask-cle: mask for CLE. Needed for executing command
39 - ti,davinci-mask-chipsel: mask for chipselect address. Needed to mask
83 ti,davinci-mask-ale = <0>;
84 ti,davinci-mask-cle = <0>;
85 ti,davinci-mask-chipsel = <0>;
/Documentation/arch/arm/samsung/
Dclksrc-change-registers.awk66 # read the header file and find the mask values that we will need
75 printf "MASK " line "\n" > "/dev/stderr"
89 mask=""
105 } else if (line ~ /\.mask/) {
106 mask = extract_value(line)
122 printf "mask '" mask "'\n" > "/dev/stderr"
128 generated = mask
135 printf "/* mask " mask " */\n"
149 printf ".shift = " dmask[mask,1] ", "
150 printf ".size = " dmask[mask,0] ", "
/Documentation/devicetree/bindings/rtc/
Dfsl,ls-ftm-alarm.yaml35 - description: bit mask of IPPDEXPCR0
36 - description: bit mask of IPPDEXPCR1
37 - description: bit mask of IPPDEXPCR2
38 - description: bit mask of IPPDEXPCR3
39 - description: bit mask of IPPDEXPCR4
40 - description: bit mask of IPPDEXPCR5
41 - description: bit mask of IPPDEXPCR6
/Documentation/devicetree/bindings/interrupt-controller/
Darm,versatile-fpga-irq.txt15 - clear-mask: a u32 number representing the mask written to clear all IRQs
17 - valid-mask: a u32 number representing a bit mask determining which of
31 clear-mask = <0xffffffff>;
32 valid-mask = <0x003fffff>;
Darm,vic.yaml42 valid-mask:
44 A one cell big bit mask of valid interrupt sources. Each bit
51 valid-wakeup-mask:
53 A one cell big bit mask of interrupt sources that can be configured
55 valid-mask property. A set bit means that this interrupt source
77 valid-mask = <0xffffff7f>;
78 valid-wakeup-mask = <0x0000ff7f>;
Dfsl,ls-extirq.yaml51 interrupt-map-mask: true
60 - interrupt-map-mask
74 interrupt-map-mask:
90 interrupt-map-mask:
113 interrupt-map-mask:
136 interrupt-map-mask = <0x7 0x0>;
/Documentation/usb/
Dusbdevfs-drop-permissions.c19 void drop_privileges(int fd, uint32_t mask) in drop_privileges() argument
23 res = ioctl(fd, USBDEVFS_DROP_PRIVILEGES, &mask); in drop_privileges()
58 uint32_t mask, caps; in main() local
87 "[3] Narrow interface permission mask\n" in main()
101 printf("Insert new mask: "); in main()
102 scanf("%x", &mask); in main()
103 drop_privileges(fd, mask); in main()
/Documentation/userspace-api/media/rc/
Dlirc-set-transmitter-mask.rst20 ``int ioctl(int fd, LIRC_SET_TRANSMITTER_MASK, __u32 *mask)``
28 ``mask``
29 Mask with channels to enable tx. Channel 0 is the least significant bit.
35 :ref:`LIRC_CAN_SET_TRANSMITTER_MASK <LIRC-CAN-SET-TRANSMITTER-MASK>` is
42 When an invalid bit mask is given, i.e. a bit is set, even though the device
/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
Dfsl,cpm1-scc-qmc.yaml92 fsl,tx-ts-mask:
98 fsl,rx-ts-mask:
132 - fsl,tx-ts-mask
133 - fsl,rx-ts-mask
169 fsl,tx-ts-mask = <0x00000000 0x000000aa>;
170 fsl,rx-ts-mask = <0x00000000 0x000000aa>;
178 fsl,tx-ts-mask = <0x00000000 0x00000055>;
179 fsl,rx-ts-mask = <0x00000000 0x00000055>;
189 fsl,tx-ts-mask = <0x00000000 0x0000ff00>;
190 fsl,rx-ts-mask = <0x00000000 0x0000ff00>;
Dfsl,qe-ucc-qmc.yaml104 fsl,tx-ts-mask:
110 fsl,rx-ts-mask:
136 - fsl,tx-ts-mask
137 - fsl,rx-ts-mask
173 fsl,tx-ts-mask = <0x00000000 0x000000aa>;
174 fsl,rx-ts-mask = <0x00000000 0x000000aa>;
182 fsl,tx-ts-mask = <0x00000000 0x00000055>;
183 fsl,rx-ts-mask = <0x00000000 0x00000055>;
193 fsl,tx-ts-mask = <0x00000000 0x0000ff00>;
194 fsl,rx-ts-mask = <0x00000000 0x0000ff00>;
Dgpio.txt17 - fsl,cpm1-gpio-irq-mask : For banks having interrupt capability (like port C
21 one as described by the fsl,cpm1-gpio-irq-mask property. There should be as
22 many interrupts as number of ones in the mask property. The first interrupt in
23 the list corresponds to the most significant bit of the mask.
45 fsl,cpm1-gpio-irq-mask = <0x0fff>;
/Documentation/devicetree/bindings/power/reset/
Dsyscon-poweroff.yaml16 with the value and mask defined in the poweroff node.
26 mask:
28 description: Update only the register bits defined by the mask (32 bit).
55 - mask
65 mask = <0x7a>;
Dsyscon-reboot.yaml16 mask defined in the reboot node. Default will be little endian mode, 32 bit
26 mask:
28 description: Update only the register bits defined by the mask (32 bit).
59 - mask
70 mask = <0x1>;
/Documentation/devicetree/bindings/mfd/
Dst,stpmic1.yaml116 st,mask-reset:
117 description: mask reset for this regulator, the regulator configuration
139 st,mask-reset:
140 description: mask reset for this regulator, the regulator configuration
161 st,mask-reset:
162 description: mask reset for this regulator, the regulator configuration
180 st,mask-reset:
181 description: mask reset for this regulator, the regulator configuration
204 st,mask-reset:
205 description: mask reset for this regulator, the regulator configuration
[all …]
/Documentation/devicetree/bindings/pinctrl/
Dpinctrl-single.yaml61 pinctrl-single,function-mask:
62 description: Mask of the allowed register bits
128 - description: bias pull up mask
137 - description: bias pull down mask
144 - description: drive strength mask
151 - description: schmitt strength mask
160 - description: input schmitt mask
167 - description: low power mode mask
174 - description: slew rate mask
201 pinctrl-single,function-mask = <0xffff>;
/Documentation/devicetree/bindings/clock/
Dkeystone-pll.txt45 - bit-shift : number of bits to shift the bit-mask
46 - bit-mask : arbitrary bitmask for programming the mux
58 bit-mask = <1>;
67 - bit-shift : number of bits to shift the bit-mask
68 - bit-mask : arbitrary bitmask for programming the divider
80 bit-mask = <8>;
/Documentation/devicetree/bindings/leds/
Dregister-bit-led.yaml36 mask:
38 bit mask for the bit controlling this LED in the register
54 - mask
73 mask = <0x01>;
82 mask = <0x02>;
90 mask = <0x04>;
/Documentation/devicetree/bindings/net/
Dmdio-mux-mmioreg.yaml33 mux-mask:
35 description: Contains an eight-bit mask that specifies which bits in the
37 child mdio-mux node must be constrained by this mask.
42 - mux-mask
54 mux-mask = <0x6>; // EMI2
/Documentation/devicetree/bindings/cpufreq/
Dnvidia,tegra20-cpufreq.txt13 1. CPU process ID mask
14 2. SoC speedo ID mask
17 1. CPU process ID mask
18 2. CPU speedo ID mask
/Documentation/arch/arm64/
Dasymmetric-32bit.rst71 affinity mask contains 64-bit-only CPUs. In this situation, the kernel
72 determines the new affinity mask as follows:
74 1. If the 32-bit-capable subset of the affinity mask is not empty,
76 mask is saved. This saved mask is inherited over ``fork(2)`` and
91 invalidate the affinity mask saved in (1) and attempt to restore the CPU
92 affinity of the task using the saved mask if it was previously valid.
98 the 32-bit-capable CPUs of the requested affinity mask. On success, the
99 affinity for the task is updated and any saved mask from a prior
/Documentation/admin-guide/perf/
Dcxl.rst35 group id and mask) config1 (threshold, filter enables) and config2 (filter
40 bit of the event mask set. More general events may be enable by setting
41 multiple mask bits in config. For example, all Device to Host Read Requests
64 $# perf stat -a -e cxl_pmu_mem0.0/vid=VID,gid=GID,mask=MASK/

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