| /Documentation/devicetree/bindings/mtd/ |
| D | fsl-upm-nand.txt | 4 - compatible : "fsl,upm-nand".
5 - reg : should specify localbus chip select and size used for the chip.
6 - fsl,upm-addr-offset : UPM pattern offset for the address latch.
7 - fsl,upm-cmd-offset : UPM pattern offset for the command latch.
10 - fsl,upm-addr-line-cs-offsets : address offsets for multi-chip support.
11 The corresponding address lines are used to select the chip.
12 - gpios : may specify optional GPIOs connected to the Ready-Not-Busy pins
13 (R/B#). For multi-chip devices, "n" GPIO definitions are required
17 - fsl,upm-wait-flags : add chip-dependent short delays after running the
20 - chip-delay : chip dependent delay for transferring data from array to
[all …]
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| /Documentation/devicetree/bindings/mfd/ |
| D | retu.txt | 1 * Device tree bindings for Nokia Retu and Tahvo multi-function device
3 Retu and Tahvo are a multi-function devices found on Nokia Internet
4 Tablets (770, N800 and N810). The Retu chip provides watchdog timer
5 and power button control functionalities while Tahvo chip provides
9 - compatible: "nokia,retu" or "nokia,tahvo"
10 - reg: Specifies the CBUS slave address of the ASIC chip
11 - interrupts: The interrupt line the device is connected to
16 compatible = "i2c-cbus-gpio";
20 interrupt-parent = <&gpio4>;
|
| D | hi6421.txt | 1 * HI6421 Multi-Functional Device (MFD), by HiSilicon Ltd.
4 - compatible : One of the following chip-specific strings:
5 "hisilicon,hi6421-pmic";
6 "hisilicon,hi6421v530-pmic";
7 - reg : register range space of hi6421;
9 Supported Hi6421 sub-devices include:
12 ------ --------- ------------ -----------
20 compatible = "hisilicon,hi6421-pmic";
26 regulator-name = "VOUT0";
27 regulator-min-microvolt = <2850000>;
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| /Documentation/devicetree/bindings/powerpc/nintendo/ |
| D | gamecube.txt | 7 This node represents the multi-function "Flipper" chip, which packages
12 - compatible : Should be "nintendo,flipper"
21 - compatible : should be "nintendo,flipper-vi"
22 - reg : should contain the VI registers location and length
23 - interrupts : should contain the VI interrupt
32 - compatible : should be "nintendo,flipper-pi"
33 - reg : should contain the PI registers location and length
37 Represents the interrupt controller within the "Flipper" chip.
43 - compatible : should be "nintendo,flipper-pic"
52 - compatible : should be "nintendo,flipper-dsp"
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| D | wii.txt | 11 - model : Should be "nintendo,wii"
12 - compatible : Should be "nintendo,wii"
16 This node represents the multi-function "Hollywood" chip, which packages
21 - compatible : Should be "nintendo,hollywood"
30 - compatible : should be "nintendo,hollywood-vi","nintendo,flipper-vi"
31 - reg : should contain the VI registers location and length
32 - interrupts : should contain the VI interrupt
41 - compatible : should be "nintendo,hollywood-pi","nintendo,flipper-pi"
42 - reg : should contain the PI registers location and length
46 Represents the "Flipper" interrupt controller within the "Hollywood" chip.
[all …]
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| /Documentation/hwmon/ |
| D | pxe1610.rst | 10 Addresses scanned: -
18 Addresses scanned: -
26 Addresses scanned: -
34 -----------
36 PXE1610/PXE1110 are Multi-rail/Multiphase Digital Controllers
39 - Intel VR13 DC-DC converter specifications.
40 - Intel SVID protocol.
44 - Servers, Workstations, and High-end desktops
46 PXM1310 is a Multi-rail Controller and it is compliant to
48 - Intel VR13 DC-DC converter specifications.
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| D | ucd9200.rst | 11 Addresses scanned: -
15 - http://focus.ti.com/lit/ds/symlink/ucd9220.pdf
16 - http://focus.ti.com/lit/ds/symlink/ucd9222.pdf
17 - http://focus.ti.com/lit/ds/symlink/ucd9224.pdf
18 - http://focus.ti.com/lit/ds/symlink/ucd9240.pdf
19 - http://focus.ti.com/lit/ds/symlink/ucd9244.pdf
20 - http://focus.ti.com/lit/ds/symlink/ucd9246.pdf
21 - http://focus.ti.com/lit/ds/symlink/ucd9248.pdf
23 Author: Guenter Roeck <linux@roeck-us.net>
27 -----------
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| D | fam15h_power.rst | 16 - BIOS and Kernel Developer's Guide (BKDG) For AMD Family 15h Processors
17 - BIOS and Kernel Developer's Guide (BKDG) For AMD Family 16h Processors
18 - AMD64 Architecture Programmer's Manual Volume 2: System Programming
23 -----------
55 On multi-node processors the calculated value is for the entire
57 attributes only for internal node0 of a multi-node processor.
111 time period (y-x). Unit of result is uWatt::
114 Jdelta = (Jy + Jmax) - Jx
116 Jdelta = Jy - Jx
117 PwrCPUave = N * Jdelta * 1000 / (Ty - Tx)
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| D | submitting-patches.rst | 10 ----------
14 - Documentation/process/submit-checklist.rst
15 - Documentation/process/submitting-patches.rst
16 - Documentation/process/coding-style.rst
18 * Please run your patch through 'checkpatch --strict'. There should be no
22 * Please use the standard multi-line comment style. Do not mix C and C++
34 hardware. In such cases, you should test-build the code on at least one
35 architecture. If run-time testing was not achieved, it should be written
43 -------------------------------------------
58 --------------
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| D | max31785.rst | 10 Addresses scanned: -
17 -----------
19 The Maxim MAX31785 is a PMBus device providing closed-loop, multi-channel fan
24 For dual-rotor configurations the MAX31785A exposes the second rotor tachometer
25 readings in attributes fan[5-8]_input. By contrast the MAX31785 only exposes
26 the slowest rotor measurement, and does so in the fan[1-4]_input attributes.
29 -----------
35 ----------------
38 fan[1-4]_alarm Fan alarm.
39 fan[1-4]_fault Fan fault.
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| /Documentation/devicetree/bindings/net/dsa/ |
| D | mediatek,mt7530.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Arınç ÜNAL <arinc.unal@arinc9.com>
11 - Landen Chao <Landen.Chao@mediatek.com>
12 - DENG Qingfang <dqfext@gmail.com>
13 - Sean Wang <sean.wang@mediatek.com>
14 - Daniel Golle <daniel@makrotopia.org>
17 There are three versions of MT7530, standalone, in a multi-chip module and
18 built-into a SoC.
[all …]
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| /Documentation/devicetree/bindings/spi/ |
| D | sprd,spi-adi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/sprd,spi-adi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Orson Zhai <orsonzhai@gmail.com>
11 - Baolin Wang <baolin.wang7@gmail.com>
12 - Chunyan Zhang <zhang.lyra@gmail.com>
15 ADI is the abbreviation of Anolog-Digital interface, which is used to access
16 analog chip (such as PMIC) from digital chip. ADI controller follows the SPI
21 48 hardware channels to access analog chip. For 2 software read/write channels,
[all …]
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| /Documentation/userspace-api/gpio/ |
| D | chardev.rst | 1 .. SPDX-License-Identifier: GPL-2.0
18 Read Documentation/driver-api/gpio/drivers-on-gpio.rst to avoid reinventing
21 Similarly, for multi-function lines there may be other subsystems, such as
23 Documentation/driver-api/pwm.rst, Documentation/w1/index.rst etc, that
28 The API is based around two major objects, the :ref:`gpio-v2-chip` and the
29 :ref:`gpio-v2-line-request`.
31 .. _gpio-v2-chip:
33 Chip chapter
36 The Chip represents a single GPIO chip and is exposed to userspace using device
39 Each chip supports a number of GPIO lines,
[all …]
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| /Documentation/sound/cards/ |
| D | cmipci.rst | 2 Brief Notes on C-Media 8338/8738/8768/8770 Driver
8 Front/Rear Multi-channel Playback
9 ---------------------------------
11 CM8x38 chip can use ADC as the second DAC so that two different stereo
13 DACs, both streams are handled independently unlike the 4/6ch multi-
22 - The first DAC supports U8 and S16LE formats, while the second DAC
24 - The second DAC supports only two channel stereo.
51 control switch in the driver "Line-In As Rear", which you can change
52 via alsamixer or somewhat else. When this switch is on, line-in jack
60 4/6 Multi-Channel Playback
[all …]
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| /Documentation/devicetree/bindings/clock/ |
| D | maxim,max77686.txt | 4 multi-function device. More information can be found in MFD DT binding
12 dt-bindings/clock/maxim,max77686.h.
17 dt-bindings/clock/maxim,max77802.h.
21 dt-bindings/clock/maxim,max77620.h.
23 Following properties should be presend in main device node of the MFD chip.
27 - #clock-cells: from common clock binding; shall be set to 1.
30 - clock-output-names: From common clock binding.
34 - 0: 32khz_ap clock (max77686, max77802), 32khz_out0 (max77620)
35 - 1: 32khz_cp clock (max77686, max77802),
36 - 2: 32khz_pmic clock (max77686).
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| /Documentation/devicetree/bindings/tpm/ |
| D | tcg,tpm-tis-mmio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/tpm/tcg,tpm-tis-mmio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MMIO-accessed Trusted Platform Module conforming to TCG TIS specification
10 - Lukas Wunner <lukas@wunner.de>
13 The Trusted Computing Group (TCG) has defined a multi-vendor standard
14 for accessing a TPM chip. It can be transported over various buses,
17 …tps://trustedcomputinggroup.org/resource/pc-client-work-group-pc-client-specific-tpm-interface-spe…
22 - enum:
[all …]
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| D | tcg,tpm_tis-spi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/tpm/tcg,tpm_tis-spi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SPI-attached Trusted Platform Module conforming to TCG TIS specification
10 - Lukas Wunner <lukas@wunner.de>
13 The Trusted Computing Group (TCG) has defined a multi-vendor standard
14 for accessing a TPM chip. It can be transported over various buses,
17 …tps://trustedcomputinggroup.org/resource/pc-client-work-group-pc-client-specific-tpm-interface-spe…
22 - enum:
[all …]
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| /Documentation/devicetree/bindings/memory-controllers/ |
| D | xlnx,zynqmp-ocmc-1.0.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/xlnx,zynqmp-ocmc-1.0.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx Zynqmp OCM(On-Chip Memory) Controller
10 - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
11 - Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
14 The OCM supports 64-bit wide ECC functionality to detect multi-bit errors
15 and recover from a single-bit memory fault.On a write, if all bytes are
17 the write-data that is written into the data RAM. If one or more bytes are
[all …]
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| D | renesas,rpc-if.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/renesas,rpc-if.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas Reduced Pin Count Interface (RPC-IF)
10 - Sergei Shtylyov <sergei.shtylyov@gmail.com>
13 Renesas RPC-IF allows a SPI flash or HyperFlash connected to the SoC to
16 The flash chip itself should be represented by a subnode of the RPC-IF node.
19 - if it contains "jedec,spi-nor", then SPI is used;
20 - if it contains "cfi-flash", then HyperFlash is used.
[all …]
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| /Documentation/networking/device_drivers/ethernet/mellanox/mlx5/ |
| D | kconfig.rst | 1 .. SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
34 | built-in into mlx5_core.ko.
39 …g (DCB) Support <https://enterprise-support.nvidia.com/s/article/howto-auto-config-pfc-and-ets-on-…
53 | Flow-based classifiers, such as those registered through
54 | `tc-flower(8)`, are processed by the device, rather than the
61 | Enables Hardware-accelerated receive flow steering (arfs) support, and ntuple filtering.
62 | https://enterprise-support.nvidia.com/s/article/howto-configure-arfs-on-connectx-4
67 | Enables :ref:`IPSec XFRM cryptography-offload acceleration <xfrm_device>`.
72 | Build support for MACsec cryptography-offload acceleration in the NIC.
83 | TLS cryptography-offload acceleration.
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| /Documentation/devicetree/bindings/mailbox/ |
| D | mediatek,gce-props.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/mediatek,gce-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Houlong Wei <houlong.wei@mediatek.com>
13 The Global Command Engine (GCE) is an instruction based, multi-threaded,
14 single-core command dispatcher for MediaTek hardware. The Command Queue
18 We use mediatek,gce-mailbox.yaml to define the properties for CMDQ mailbox
28 mediatek,gce-events:
32 The property mediatek,gce-events is used to obtain the event IDs.
[all …]
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| /Documentation/devicetree/bindings/ |
| D | trivial-devices.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/trivial-devices.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
27 spi-max-frequency: true
32 - enum:
34 - acbel,fsg032
35 … # SMBus/I2C Digital Temperature Sensor in 6-Pin SOT with SMBus Alert and Over Temperature Pin
36 - ad,ad7414 # Deprecated, use adi,ad7414
[all …]
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| /Documentation/devicetree/bindings/phy/ |
| D | apm-xgene-phy.txt | 1 * APM X-Gene 15Gbps Multi-purpose PHY nodes
3 PHY nodes are defined to describe on-chip 15Gbps Multi-purpose PHY. Each
7 - compatible : Shall be "apm,xgene-phy".
8 - reg : PHY memory resource is the SDS PHY access resource.
9 - #phy-cells : Shall be 1 as it expects one argument for setting
14 - status : Shall be "ok" if enabled or "disabled" if disabled.
16 - clocks : Reference to the clock entry.
17 - apm,tx-eye-tuning : Manual control to fine tune the capture of the serial
19 Two set of 3-tuple setting for each (up to 3)
22 - apm,tx-eye-direction : Eye tuning manual control direction. 0 means sample
[all …]
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| /Documentation/userspace-api/media/ |
| D | glossary.rst | 1 .. SPDX-License-Identifier: GPL-2.0 OR GFDL-1.1-no-invariants-or-later
58 **Field-programmable Gate Array**
63 See https://en.wikipedia.org/wiki/Field-programmable_gate_array.
72 together make a larger user-facing functional peripheral. For
80 **Inter-Integrated Circuit**
82 A multi-master, multi-slave, packet switched, single-ended,
84 like sub-device hardware components.
86 See http://www.nxp.com/docs/en/user-guide/UM10204.pdf.
94 Also known as chip.
120 - :term:`CEC API`;
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| /Documentation/fb/ |
| D | viafb.rst | 2 VIA Integration Graphic Chip Console Framebuffer Driver
6 --------
15 ---------------
34 ----------------------
47 - 640x480 (default)
48 - 720x480
49 - 800x600
50 - 1024x768
53 - 8, 16, 32 (default:32)
56 - 60, 75, 85, 100, 120 (default:60)
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|