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/Documentation/devicetree/bindings/gpu/host1x/
Dnvidia,tegra234-nvdec.yaml70 nvidia,bl-manifest-offset:
73 Offset to bootloader manifest from beginning of firmware that was configured by
76 nvidia,bl-code-offset:
79 Offset to bootloader code section from beginning of firmware that was configured by
82 nvidia,bl-data-offset:
85 Offset to bootloader data section from beginning of firmware that was configured by
88 nvidia,os-manifest-offset:
91 Offset to operating system manifest from beginning of firmware that was configured by
94 nvidia,os-code-offset:
97 Offset to operating system code section from beginning of firmware that was configured by
[all …]
/Documentation/devicetree/bindings/net/
Ddavinci_emac.txt9 - reg: Offset and length of the register set for the device
10 - ti,davinci-ctrl-reg-offset: offset to control register
11 - ti,davinci-ctrl-mod-reg-offset: offset to control module register
12 - ti,davinci-ctrl-ram-offset: offset to control module ram
33 ti,davinci-ctrl-reg-offset = <0x3000>;
34 ti,davinci-ctrl-mod-reg-offset = <0x2000>;
35 ti,davinci-ctrl-ram-offset = <0>;
/Documentation/devicetree/bindings/reset/
Dintel,rcu-gw.yaml23 description: Global reset register offset and bit offset.
26 - description: Register offset
27 - description: Register bit offset
35 First cell is reset request register offset.
36 Second cell is bit offset in reset request register.
37 Third cell is bit offset in reset status register.
38 For LGM SoC, reset cell count is 2 as bit offset in
40 3 for legacy SoCs as bit offset differs.
/Documentation/ABI/testing/
Dsysfs-bus-iio-adc-mt63606 Calculating with scale and offset returns voltage in uV
14 Calculating with scale and offset returns voltage in uV
22 Calculating with scale and offset returns voltage in uV
29 Calculating with scale and offset returns voltage in uV
36 Calculating with scale and offset returns voltage in uV
43 Calculating with scale and offset returns voltage in uA
50 Calculating with scale and offset returns voltage in uA
57 Calculating with scale and offset returns voltage in uV
64 Calculating with scale and offset returns temperature in degree
71 Calculating with scale and offset returns voltage in uV
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Dsysfs-bus-iio-adc-mcp356423 include an offset cancellation algorithm that cancels the offset
24 contribution of the ADC). When the offset cancellation algorithm
29 cancellation of the ADC offset error and the achievement of
30 ultra-low offset without any digital calibration. The resulting
31 offset is the residue of the difference between the two
33 floor. This offset is effectively canceled at every conversion,
34 so the residual offset error temperature drift is extremely low.
50 offset value of the reference buffer. As a result, the SNR of
Ddebugfs-tpmi8 tpmi_id, number of entries, entry size, offset, vsec offset, lock status
25 Allows to write at any offset. It doesn't check for Read/Write access
27 at offset multiples of 4. The format is instance,offset,contents.
/Documentation/trace/
Duprobetracer.rst19 user to calculate the offset of the probepoint in the object.
29 p[:[GRP/][EVENT]] PATH:OFFSET [FETCHARGS] : Set a uprobe
30 r[:[GRP/][EVENT]] PATH:OFFSET [FETCHARGS] : Set a return uprobe (uretprobe)
31 p[:[GRP/][EVENT]] PATH:OFFSET%return [FETCHARGS] : Set a return uprobe (uretprobe)
36 on PATH+OFFSET.
38 OFFSET : Offset where the probe is inserted.
39 OFFSET%return : Offset where the return probe is inserted.
44 @+OFFSET : Fetch memory at OFFSET (OFFSET from same file as PATH)
72 offset, and container-size (usually 32). The syntax is::
74 b<bit-width>@<bit-offset>/<container-size>
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/Documentation/devicetree/bindings/arm/hisilicon/controller/
Dsysctrl.yaml19 offset. In addition, the HiP01 system controller has some specific control
54 smp-offset:
56 offset in sysctrl for notifying slave cpu booting
63 resume-offset:
64 description: offset in sysctrl for notifying cpu0 when resume
67 reboot-offset:
68 description: offset in sysctrl for system reboot
119 smp-offset = <0x31c>;
120 resume-offset = <0x308>;
121 reboot-offset = <0x4>;
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/Documentation/devicetree/bindings/mtd/
Dfsl-upm-nand.txt6 - fsl,upm-addr-offset : UPM pattern offset for the address latch.
7 - fsl,upm-cmd-offset : UPM pattern offset for the command latch.
33 fsl,upm-addr-offset = <16>;
34 fsl,upm-cmd-offset = <8>;
53 fsl,upm-addr-offset = <0x10>;
54 fsl,upm-cmd-offset = <0x08>;
/Documentation/leds/
Dleds-mlxcpld.rst28 - CPLD reg offset: 0x20
32 - CPLD reg offset: 0x20
36 - CPLD reg offset: 0x21
40 - CPLD reg offset: 0x21
44 - CPLD reg offset: 0x22
48 - CPLD reg offset: 0x22
77 - CPLD reg offset: 0x20
81 - CPLD reg offset: 0x21
85 - CPLD reg offset: 0x23
89 - CPLD reg offset: 0x23
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/Documentation/devicetree/bindings/display/msm/
Ddsi-phy-10nm.yaml38 qcom,phy-rescode-offset-top:
42 Integer array of offset for pull-up legs rescode for all five lanes.
43 To offset the drive strength from the calibrated value in an increasing
49 qcom,phy-rescode-offset-bot:
53 Integer array of offset for pull-down legs rescode for all five lanes.
54 To offset the drive strength from the calibrated value in a decreasing
64 for the HSTX drive. Use supported levels (mV) to offset the drive level
97 qcom,phy-rescode-offset-top = /bits/ 8 <0 0 0 0 0>;
98 qcom,phy-rescode-offset-bot = /bits/ 8 <0 0 0 0 0>;
/Documentation/devicetree/bindings/mtd/partitions/
Dtplink,safeloader-partitions.yaml24 This binding describes partitioning method and defines offset of ASCII
25 based partitions table. That offset is picked at manufacturing process
35 partitions-table-offset:
36 description: Flash offset of partitions table
44 - partitions-table-offset
52 partitions-table-offset = <0x100000>;
/Documentation/devicetree/bindings/phy/
Dstarfive,jh7110-pcie-phy.yaml27 - description: PHY connect offset of SYS_SYSCONSAIF__SYSCFG register for USB PHY.
29 The phandle to System Register Controller syscon node and the PHY connect offset
37 - description: PHY mode offset of STG_SYSCONSAIF__SYSCFG register.
38 - description: PHY enable for USB offset of STG_SYSCONSAIF__SYSCFG register.
40 The phandle to System Register Controller syscon node and the offset
41 of STG_SYSCONSAIF__SYSCFG register for PCIe PHY. Total 2 regsisters offset.
/Documentation/devicetree/bindings/display/
Dxylon,logicvc-display.yaml25 In version 3 of the controller, each layer has fixed memory offset and address
112 Configuration of layers' size, position and offset is enabled
153 xylon,layer-base-offset:
156 Offset in number of lines (C_LAYER_X_OFFSET) starting from the
159 xylon,layer-buffer-offset:
162 Offset in number of lines (C_BUFFER_*_OFFSET) starting from the
163 layer base offset for the second buffer used in double-buffering.
249 xylon,layer-base-offset = <0>;
250 xylon,layer-buffer-offset = <480>;
259 xylon,layer-base-offset = <2400>;
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/Documentation/devicetree/bindings/clock/
Darm,syscon-icst.yaml19 an ICST clock request after a write to the 32 bit register at an offset
22 writing a special token to another offset in the system controller.
83 lock-offset:
85 description: Offset to the unlocking register for the oscillator
87 vco-offset:
89 description: Offset to the VCO register for the oscillator
104 lock-offset = <0x08>;
105 vco-offset = <0x00>;
Dxgene.txt49 - csr-offset : Offset to the CSR reset register from the reset address base.
52 - enable-offset : Offset to the enable register from the reset address base.
55 - divider-offset : Offset to the divider CSR register from the divider base.
107 divider-offset = <0x238>;
121 csr-offset = <0x0>;
123 enable-offset = <0x8>;
125 divider-offset = <0x10>;
/Documentation/devicetree/bindings/regulator/
Danatop-regulator.yaml21 anatop-reg-offset:
23 description: u32 value representing the anatop MFD register offset.
45 anatop-delay-reg-offset:
47 description: u32 value representing the anatop MFD step time register offset.
59 description: u32 value representing regulator enable bit offset.
67 - anatop-reg-offset
84 anatop-reg-offset = <0x140>;
87 anatop-delay-reg-offset = <0x170>;
/Documentation/bpf/
Dllvm_reloc.rst17 Elf64_Addr r_offset; // Offset from the beginning of section.
55 Relocation section '.rel.text' at offset 0x190 contains 4 entries:
56 Offset Info Type Symbol's Value Symbol's Name
62 Each relocation is represented by ``Offset`` (8 bytes) and ``Info`` (8 bytes).
64 (Offset 0x0) and the corresponding ``Info`` indicates the relocation type
81 Similarly, the second relocation is at ``.text`` offset ``0x18``, instruction 3,
84 value 4. The symbol value represents the offset from the start of ``.data``
92 the section offset is written to the original insn
94 above insn ``7`` and ``11``, they have section offset ``8`` and ``12``.
99 and is the section offset or some computation result based on
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/Documentation/devicetree/bindings/power/reset/
Dsyscon-reboot-mode.yaml17 parental dt-node plus the offset. So the SYSCON reboot-mode node
28 offset:
30 description: Offset in the register map for the mode register (in bytes)
39 - offset
47 offset = <0x40>;
Dsyscon-poweroff.yaml15 defined by the register map pointed by syscon reference plus the offset
30 offset:
32 description: Offset in the register map for the poweroff register (in bytes).
47 - offset
64 offset = <0x0>;
/Documentation/devicetree/bindings/iio/afe/
Dtemperature-transducer.yaml26 T = (Isense(T) / alpha) + offset
27 T = 1 / (Rsense * alpha) * (V + offset * Rsense * alpha)
64 sense-offset-millicelsius:
66 Temperature offset.
67 This offset is commonly used to convert from Kelvins to degrees Celsius.
68 In that case, sense-offset-millicelsius would be set to <(-273150)>.
101 sense-offset-millicelsius = <(-273150)>; /* Kelvin to degrees Celsius */
111 sense-offset-millicelsius = <(-273150)>; /* Kelvin to degrees Celsius */
/Documentation/admin-guide/device-mapper/
Ddelay.rst10 <device> <offset> <delay> [<write_device> <write_offset> <write_delay>
15 3: apply offset and delay to read, write and flush operations on device
17 6: apply offset and delay to device, also apply write_offset and write_delay
19 optionally different sector offset
52 # onto the same backing device at offset 0 sectors.
/Documentation/devicetree/bindings/auxdisplay/
Dimg,ascii-lcd.yaml22 offset:
25 Offset in bytes to the LCD registers within the system controller
34 - offset
46 - offset
/Documentation/devicetree/bindings/mmc/
Dnvidia,tegra20-sdhci.yaml112 nvidia,pad-autocal-pull-down-offset-1v8:
117 nvidia,pad-autocal-pull-down-offset-1v8-timeout:
122 nvidia,pad-autocal-pull-down-offset-3v3:
127 nvidia,pad-autocal-pull-down-offset-3v3-timeout:
132 nvidia,pad-autocal-pull-down-offset-sdr104:
136 nvidia,pad-autocal-pull-down-offset-hs400:
140 nvidia,pad-autocal-pull-up-offset-1v8:
145 nvidia,pad-autocal-pull-up-offset-1v8-timeout:
150 nvidia,pad-autocal-pull-up-offset-3v3:
162 nvidia,pad-autocal-pull-up-offset-3v3-timeout:
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/Documentation/devicetree/bindings/input/touchscreen/
Dedt-ft5x06.yaml31 offset-x: true
32 offset-y: true
72 offset:
78 offset-x:
79 description: Same as offset, but applies only to the horizontal position.
85 offset-y:
86 description: Same as offset, but applies only to the vertical position.

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