| /Documentation/userspace-api/media/v4l/ |
| D | tuner.rst | 13 Video input devices can have one or more tuners demodulating a RF
14 signal. Each tuner is associated with one or more video inputs,
21 Radio input devices have exactly one tuner with index zero, no video
34 current tuner, when there is more than one. The tuner is solely
38 device has one or more tuners.
44 Video output devices can have one or more modulators, that modulate a
46 set or video recorder. Each modulator is associated with one or more
54 Radio output devices have exactly one modulator with index zero, no
58 separate device nodes will have to be used for such hardware, one that
59 supports the tuner functionality and one that supports the modulator
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| D | pixfmt-compressed.rst | 44 The decoder expects one Access Unit per buffer.
45 The encoder generates one Access Unit per buffer.
77 Exactly one output and one capture buffer must be provided for use
127 Exactly one output and one capture buffer must be provided for use with
155 - VP8 compressed video frame. The encoder generates one
156 compressed frame per buffer, and the decoder requires one
168 Exactly one output and one capture buffer must be provided for use with
177 - VP9 compressed video frame. The encoder generates one
178 compressed frame per buffer, and the decoder requires one
191 Exactly one output and one capture buffer must be provided for use with
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | sprd,pinctrl.txt | 6 register contains several bit fields with one bit or several bits
9 driving level": One pin can output 3.0v or 1.8v, depending on the
12 to choose one function (like: UART0) for which system, since we
13 have several systems (AP/CP/CM4) on one SoC.).
17 as one generic configuration, and maybe it will add more strange
18 global configuration in future. Then we add one "sprd,control" to
22 Moreover we recognise every fields comprising one bit or several
23 bits in one global control register as one pin, thus we should
28 register definition, and each register described one pin is used
57 register definition, and each register described one pin is used to
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| /Documentation/devicetree/bindings/usb/ |
| D | gr-udc.txt | 15 - interrupts : Interrupt numbers for this device. Either one interrupt number
16 for all interrupts, or one for status related interrupts, one for IN
17 endpoint related interrupts and one for OUT endpoint related interrupts.
23 number. If the property is present it typically contains one entry for
29 number. If the property is present it typically contains one entry for
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| D | brcm,usb-pinmap.yaml | 27 description: Array of one or two GPIO pins used for input signals.
31 description: Array of input signal names, one per gpio in in-gpios.
35 description: Array of enable and mask pairs, one per gpio in-gpios.
39 description: Array of one GPIO pin used for output signals.
43 description: Array of output signal names, one per gpio in out-gpios.
47 description: Array of enable, value, changed and clear masks, one
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| /Documentation/ABI/testing/ |
| D | debugfs-scmi-raw | 11 Each write to the entry causes one command request to be built
12 and sent while the replies are read back one message at time
29 Each write to the entry causes one command request to be built
30 and sent while the replies are read back one message at time
41 Each read gives back one message at time (receiving an EOF at
52 Each read gives back one message at time (receiving an EOF at
80 Each write to the entry causes one command request to be built
81 and sent while the replies are read back one message at time
89 one default channel.
107 Each write to the entry causes one command request to be built
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| /Documentation/devicetree/bindings/iommu/ |
| D | samsung,sysmmu.yaml | 23 System MMUs are in many to one relation with peripheral devices, i.e. single
24 peripheral device might have multiple System MMUs (usually one for each bus
25 master), but one System MMU can handle transactions from only one peripheral
31 * MFC has one System MMU on its left and right bus.
32 * FIMD in Exynos5420 has one System MMU for window 0 and 4, the other system MMU
34 * M2M Scalers and G2D in Exynos5420 has one System MMU on the read channel and
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| /Documentation/devicetree/bindings/phy/ |
| D | realtek,usb3phy.yaml | 16 support multiple XHCI controllers. One PHY device node maps to one XHCI
21 Each XHCI maps to one USB 2.0 PHY and map one USB 3.0 PHY on some
31 Each XHCI maps to one USB 2.0 PHY and map one USB 3.0 PHY on controllers#2.
39 Each xhci maps to one USB 2.0 PHY and map one USB 3.0 PHY on controllers#0.
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| D | realtek,usb2phy.yaml | 16 support multiple XHCI controllers. One PHY device node maps to one XHCI
21 Each XHCI maps to one USB 2.0 PHY and map one USB 3.0 PHY on some
31 The controller#0 has one USB 2.0 PHY. The controller#1 includes two USB 2.0
39 Each XHCI maps to one USB 2.0 PHY and map one USB 3.0 PHY on controllers#2.
47 Each xhci maps to one USB 2.0 PHY and map one USB 3.0 PHY on controllers#0.
55 Each XHCI maps to one USB 2.0 PHY.
98 For one of the phys of RTD1619b SoC, the synchronous clock of the
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| D | brcm,stingray-usb-phy.txt | 4 - compatible : should be one of the listed compatibles
5 - "brcm,sr-usb-combo-phy" is combo PHY has two PHYs, one SS and one HS.
9 - Must be 1 for brcm,sr-usb-combo-phy as it expects one argument to indicate
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| /Documentation/devicetree/bindings/timer/ |
| D | xlnx,xps-timer.yaml | 38 xlnx,one-timer-only:
42 Whether only one timer is present in this block.
47 - xlnx,one-timer-only
58 xlnx,one-timer-only:
81 xlnx,one-timer-only = <0x0>;
91 xlnx,one-timer-only = <0x0>;
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| /Documentation/devicetree/bindings/sound/ |
| D | mvebu-audio.txt | 15 (named "pll_regs") and the second one ("soc_ctrl") - for register
16 where one of exceptive I/O types (I2S or S/PDIF) is set.
23 - clocks: one or two phandles.
24 The first one is mandatory and defines the internal clock.
25 The second one is optional and defines an external clock.
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| /Documentation/userspace-api/media/mediactl/ |
| D | media-types.rst | 144 composing must have at least two sink pads and one source
152 must have at least one sink pad and one source pad. Read
161 encoding conversion must have at least one sink pad and one
170 processing must have one sink pad and one source pad. It uses
179 at least one sink pad and one source pad, and scale the
184 scaling can be supported in one direction only). Binning and
190 capable of statistics computation must have one sink pad and
191 one source pad. It computes statistics over the frames
197 compressing video frames. Must have one sink pad and at least
198 one source pad.
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| /Documentation/filesystems/ |
| D | inotify.rst | 39 want: Users initialize inotify, once, and add n watches, requiring but one
57 versus just one. It is a lot messier in the kernel. A single, linear
72 Additionally, it _is_ possible to more than one instance and
73 juggle more than one queue and thus more than one associated fd. There
74 need not be a one-fd-per-process mapping; it is one-fd-per-queue and a
75 process can easily want more than one queue.
84 file descriptor-based one that allows basic file I/O and poll/select.
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| /Documentation/sound/soc/ |
| D | jack.rst | 9 - It allows more than one jack detection method to work together on one
24 mechanisms, one for the headphone and one for the microphone. Some
60 also available, for example integrated into CODECs. One example of
64 least one to be useful.
71 the list of pins to update then set up one or more jack detection
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| /Documentation/devicetree/bindings/powerpc/4xx/ |
| D | cpm.txt | 10 one of two different order for the CPM
16 - unused-units : specifier consist of one cell. For each
20 - idle-doze : specifier consist of one cell. For each
24 - standby : specifier consist of one cell. For each
28 - suspend : specifier consist of one cell. For each
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| /Documentation/devicetree/bindings/display/bridge/ |
| D | megachips-stdpxxxx-ge-b850v3-fw.txt | 16 two bridges behaves as a single one. The only interfaces exposed by the
22 - interrupts : one interrupt should be described here, as in
24 - ports : One input port(reg = <0>) and one output port(reg = <1>)
29 - ports : One input port(reg = <0>) and one output port(reg = <1>)
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| /Documentation/devicetree/bindings/mux/ |
| D | mux-controller.yaml | 13 A multiplexer (or mux) controller will have one, or several, consumer devices
15 several parallel multiplexers. Presumably there will be at least one
29 The value of '#mux-state-cells' will always be one greater than the value
36 idle-state property is an array with one idle state for each mux controller.
40 mux controller chips with more than one mux controller, particularly when
94 controllers, the idle-state property is an array with one idle state for
99 mux controller chips with more than one mux controller, particularly when
116 /* One consumer of a 2-way mux controller (one GPIO-line) */
139 * Two consumers (one for an ADC line and one for an i2c bus) of
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| /Documentation/devicetree/bindings/pci/ |
| D | cdns-pcie.yaml | 15 One per lane if more than one in the list. If only one PHY listed it must
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | abilis,tb10x-ictl.txt | 5 one-to-one mapping of external interrupt sources to CPU interrupts and
18 are mapped one-to-one to parent interrupts.
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| /Documentation/ABI/obsolete/ |
| D | sysfs-driver-hid-roccat-ryos | 4 Description: When written, this file lets one select which data from which
24 Description: When written, this file lets one set the default of all keys for
34 Description: When written, this file lets one set the function of the
44 Description: When written, this file lets one set the function of the macro
54 Description: When written, this file lets one set the function of the
64 Description: When written, this file lets one set the function of the
74 Description: When written, this file lets one set the function of the
84 Description: When written, this file lets one deactivate certain keys like
95 Description: When written, this file lets one set the backlight intensity for
106 Description: When written, this file lets one store macros with max 480
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| /Documentation/devicetree/bindings/spi/ |
| D | sprd,spi-adi.yaml | 24 which means we can just link one analog chip address to one hardware channel,
28 Thus we introduce one property named "sprd,hw-channels" to configure hardware
34 one system is reading/writing data by ADI software channels, that should be under
35 one hardware spinlock protection to prevent other systems from reading/writing
38 Then we need one hardware spinlock to synchronize between the multiple subsystems.
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| /Documentation/driver-api/media/drivers/ |
| D | bttv-devel.rst | 18 log, telling which card type is used. Like this one::
28 new entries which are not listed yet. If there isn't one for your
29 card, you can check if one of the existing entries does work for you
34 example. If your board has one, you might have to load a helper
35 module like ``msp3400`` to make sound work. If there isn't one for the
36 chip used on your board: Bad luck. Start writing a new one. Well,
51 these pins. One register is the output enable register
53 bt848 chip. Another one is the data register (``BT848_GPIO_DATA``), where
103 audioall=a set the values of the audiomux array (one
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| /Documentation/bpf/ |
| D | map_cgroup_storage.rst | 131 for a single ``CGROUP_STORAGE`` map, there can be at most one program loaded
136 There is a one-to-one association between the map of each type (per-CPU and
138 each map can only be used by one BPF program and each BPF program can only use
139 one storage map of each type. Because of map can only be used by one BPF
153 However, the BPF program can still only associate with one map of each type
154 (per-CPU and non-per-CPU). A BPF program cannot use more than one
155 ``BPF_MAP_TYPE_CGROUP_STORAGE`` or more than one
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| /Documentation/devicetree/bindings/mailbox/ |
| D | brcm,iproc-flexrm-mbox.txt | 5 hardware blocks. There is one device tree entry per FlexRM block. The
16 interrupts) to CPU. There is one MSI for each FlexRM ring.
25 one MSI interrupt to CPU.
31 specified by this cell then it will inject one MSI interrupt
32 to CPU provided at least one completion message is available.
|