Searched full:p4080 (Results 1 – 12 of 12) sorted by relevance
| /Documentation/devicetree/bindings/powerpc/fsl/ |
| D | ccf.txt | 15 Example chips: P5040, P5020, P4080, P3041, P2041
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| D | dcsr.txt | 224 compatible = "fsl,p4080-dcsr-dpaa", "fsl,dcsr-dpaa";
252 compatible = "fsl,p4080-dcsr-ocn", "fsl,dcsr-ocn";
312 compatible = "fsl,p4080-dcsr-nal", "fsl,dcsr-nal";
342 compatible = "fsl,p4080-dcsr-rcpm", "fsl,dcsr-rcpm";
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| D | srio.txt | 63 For HW (ie, the P4080) that only supports a LIODN for both
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| D | mpic.txt | 228 compatible = "fsl,p4080-memory-controller";
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| D | dma.txt | 71 mpc8540, mpc8641 p4080, bsc9131 etc.
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| /Documentation/devicetree/bindings/crypto/ |
| D | fsl,sec-v4.0.yaml | 26 such as the P4080. The number of simultaneous dequeues the QI can make is
28 SEC version. E.g., the SEC 4.0 in the P4080 has 5 DECOs and can thus
34 in the memory partition devoted to a particular core. The P4080 has 4 JRs, so
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| /Documentation/devicetree/bindings/net/ |
| D | fsl,fman.yaml | 40 - P2041, P3041, P4080 P5020, P5040:
45 (Second FM available only in P4080 and P5040)
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| D | fsl,fman-dtsec.yaml | 52 - P2041, P3041, P4080 P5020, P5040:
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| /Documentation/devicetree/bindings/clock/ |
| D | fsl,qoriq-clock.yaml | 25 1.0 p4080, p5020, p5040
40 - fsl,p4080-clockgen
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| /Documentation/devicetree/bindings/mmc/ |
| D | fsl,esdhc.yaml | 23 - fsl,p4080-esdhc
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| /Documentation/devicetree/bindings/soc/fsl/ |
| D | fsl,rcpm.yaml | 23 - fsl,p4080-rcpm
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| /Documentation/networking/device_drivers/ethernet/freescale/ |
| D | dpaa.rst | 101 - P4080
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