Searched +full:pci +full:- +full:based (Results 1 – 25 of 207) sorted by relevance
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| /Documentation/admin-guide/media/ |
| D | pci-cardlist.rst | 1 .. SPDX-License-Identifier: GPL-2.0
3 PCI drivers
6 The PCI boards are identified by an identification called PCI ID. The PCI ID
9 - Vendor ID and device ID;
10 - Subsystem ID and Subsystem device ID;
12 The ``lspci -nn`` command allows identifying the vendor/device PCI IDs:
14 .. code-block:: none
15 :emphasize-lines: 3
17 $ lspci -nn
23 …02:02.0 Multimedia video controller [0400]: Conexant Systems, Inc. CX23418 Single-Chip MPEG-2 Enco…
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| D | technisat.rst | 1 .. SPDX-License-Identifier: GPL-2.0
13 -----------------------------
19 .. code-block:: none
21 lspci -vvv for a PCI device (lsusb -vvv for an USB device) will show you for example:
29 -------------------
37 (except ``Simple tuner support`` for ATSC 3rd generation only -> see case 9 please).
41 - Main module part:
45 #) => ``Technisat/B2C2 Air/Sky/Cable2PC PCI`` (PCI card) or
50 - Frontend / Tuner / Demodulator module part:
55 - SkyStar DVB-S Revision 2.3:
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| D | bt8xx.rst | 1 .. SPDX-License-Identifier: GPL-2.0
16 -------------------
18 This class of cards has a bt878a as the PCI interface, and require the bttv
21 Please see Documentation/admin-guide/media/bttv-cardlist.rst for a complete
22 list of Cards based on the Conexant Bt8xx PCI bridge supported by the
28 ./scripts/config -e PCI
29 ./scripts/config -e INPUT
30 ./scripts/config -m I2C
31 ./scripts/config -m MEDIA_SUPPORT
32 ./scripts/config -e MEDIA_PCI_SUPPORT
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| /Documentation/devicetree/bindings/pci/ |
| D | brcm,iproc-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/brcm,iproc-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ray Jui <ray.jui@broadcom.com>
11 - Scott Branden <scott.branden@broadcom.com>
14 - $ref: /schemas/pci/pci-host-bridge.yaml#
19 - enum:
20 # for the first generation of PAXB based controller, used in SoCs
22 - brcm,iproc-pcie
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| D | host-generic-pci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/host-generic-pci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic PCI host controller
10 - Will Deacon <will@kernel.org>
13 Firmware-initialised PCI host controllers and PCI emulations, such as the
14 virtio-pci implementations found in kvmtool and other para-virtualised
21 Configuration Space is assumed to be memory-mapped (as opposed to being
23 geography of a PCI bus address by concatenating the various components to
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| D | rockchip-dw-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip-dw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: DesignWare based PCIe Root Complex controller on Rockchip SoCs
10 - Shawn Lin <shawn.lin@rock-chips.com>
11 - Simon Xue <xxm@rock-chips.com>
12 - Heiko Stuebner <heiko@sntech.de>
15 RK3568 SoC PCIe Root Complex controller is based on the Synopsys DesignWare
17 snps,dw-pcie.yaml.
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| D | pcie-al.txt | 3 Amazon's Annapurna Labs PCIe Host Controller is based on the Synopsys DesignWare
4 PCI core. It inherits common properties defined in
5 Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
9 - compatible:
13 - "amazon,al-alpine-v2-pcie" for alpine_v2
14 - "amazon,al-alpine-v3-pcie" for alpine_v3
16 - reg:
18 Value type: <prop-encoded-array>
19 Definition: Register ranges as listed in the reg-names property
21 - reg-names:
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| D | rockchip-dw-pcie-ep.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip-dw-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: DesignWare based PCIe Endpoint controller on Rockchip SoCs
10 - Niklas Cassel <cassel@kernel.org>
13 RK3588 SoC PCIe Endpoint controller is based on the Synopsys DesignWare
15 snps,dw-pcie-ep.yaml.
18 - $ref: /schemas/pci/snps,dw-pcie-ep.yaml#
19 - $ref: /schemas/pci/rockchip-dw-pcie-common.yaml#
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| D | amlogic,axg-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/amlogic,axg-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Neil Armstrong <neil.armstrong@linaro.org>
13 Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core.
16 - $ref: /schemas/pci/pci-host-bridge.yaml#
17 - $ref: /schemas/pci/snps,dw-pcie-common.yaml#
19 # We need a select here so we don't match all nodes with 'snps,dw-pcie'
24 - amlogic,axg-pcie
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| D | socionext,uniphier-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/socionext,uniphier-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 UniPhier PCIe host controller is based on the Synopsys DesignWare
11 PCI core. It shares common features with the PCIe DesignWare core and
13 Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
19 - $ref: /schemas/pci/snps,dw-pcie.yaml#
24 - socionext,uniphier-pcie
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| D | socionext,uniphier-pcie-ep.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/socionext,uniphier-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 UniPhier PCIe endpoint controller is based on the Synopsys DesignWare
11 PCI core. It shares common features with the PCIe DesignWare core and
13 Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
21 - socionext,uniphier-pro5-pcie-ep
22 - socionext,uniphier-nx1-pcie-ep
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| /Documentation/PCI/ |
| D | msi-howto.rst | 1 .. SPDX-License-Identifier: GPL-2.0
17 to change your driver to use MSI or MSI-X and some basic diagnostics to
27 The MSI capability was first specified in PCI 2.2 and was later enhanced
28 in PCI 3.0 to allow each interrupt to be masked individually. The MSI-X
29 capability was also introduced with PCI 3.0. It supports more interrupts
32 Devices may support both MSI and MSI-X, but only one can be enabled at
40 traditional pin-based interrupts.
42 Pin-based PCI interrupts are often shared amongst several devices.
47 When a device writes data to memory, then raises a pin-based interrupt,
49 arrived in memory (this becomes more likely with devices behind PCI-PCI
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| /Documentation/networking/devlink/ |
| D | devlink-eswitch-attr.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 Devlink E-Switch Attribute
7 Devlink E-Switch supports two modes of operation: legacy and switchdev.
8 Legacy mode operates based on traditional MAC/VLAN steering rules. Switching
9 decisions are made based on MAC addresses, VLANs, etc. There is limited ability
13 capabilities of the E-Switch to hardware. In switchdev mode, more switching
16 or scalable-functions (SFs) of the device. See more information about
20 In addition, the devlink E-Switch also comes with other attributes listed
26 The following is a list of E-Switch attributes.
28 .. list-table:: E-Switch attributes
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| D | devlink-port.rst | 1 .. SPDX-License-Identifier: GPL-2.0
9 ``devlink-port`` is a port that exists on the device. It has a logically
19 .. list-table:: List of devlink port flavours
22 * - Flavour
23 - Description
24 * - ``DEVLINK_PORT_FLAVOUR_PHYSICAL``
25 - Any kind of physical port. This can be an eswitch physical port or any
27 * - ``DEVLINK_PORT_FLAVOUR_DSA``
28 - This indicates a DSA interconnect port.
29 * - ``DEVLINK_PORT_FLAVOUR_CPU``
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| /Documentation/PCI/endpoint/ |
| D | pci-endpoint.rst | 1 .. SPDX-License-Identifier: GPL-2.0
5 This document is a guide to use the PCI Endpoint Framework in order to create
12 Linux has a comprehensive PCI subsystem to support PCI controllers that
13 operates in Root Complex mode. The subsystem has capability to scan PCI bus,
14 assign memory resources and IRQ resources, load PCI driver (based on
15 vendor ID, device ID), support other services like hot-plug, power management,
18 However the PCI controller IP integrated in some SoCs is capable of operating
19 either in Root Complex mode or Endpoint mode. PCI Endpoint Framework will
22 validation, co-processor accelerator, etc.
24 PCI Endpoint Core
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| /Documentation/arch/arm/ |
| D | ixp4xx.rst | 6 -------------------------------------------------------------------------
17 integration such as an on-chip I2C controller.
30 - Dual serial ports
31 - PCI interface
32 - Flash access (MTD/JFFS)
33 - I2C through GPIO on IXP42x
34 - GPIO for input/output/interrupts
35 See arch/arm/mach-ixp4xx/include/mach/platform.h for access functions.
36 - Timers (watchdog, OS)
41 - USB device interface
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| /Documentation/scsi/ |
| D | BusLogic.rst | 1 .. SPDX-License-Identifier: GPL-2.0
21 Copyright 1995-1998 by Leonard N. Zubkoff <lnz@dandelion.com>
57 BT-948/958/958D, will always be available from my Linux Home Page at URL
69 the BT-948 PCI Ultra SCSI Host Adapter, and then again for the BT-958 PCI Wide
80 Linux community, and I am now working on a Linux driver for the DAC960 PCI RAID
90 94555, USA and can be reached at 510/796-6100 or on the World Wide Web at
92 mail at techsup@mylex.com, by Voice at 510/608-2400, or by FAX at 510/745-7715.
101 -----------------------------------
116 adapter will attempt to negotiate for 20.0 mega-transfers/second.
121 adapter will attempt to negotiate for 10.0 mega-transfers/second.
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| D | advansys.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 RISC-based, Bus-Mastering, Fast (10 Mhz) and Ultra (20 Mhz) Narrow
9 (8-bit transfer) SCSI Host Adapters for the ISA, EISA, VL, and PCI
10 buses and RISC-based, Bus-Mastering, Ultra (20 Mhz) Wide (16-bit
11 transfer) SCSI Host Adapters for the PCI bus.
21 - ABP-480 - Bus-Master CardBus (16 CDB)
24 - ABP510/5150 - Bus-Master ISA (240 CDB)
25 - ABP5140 - Bus-Master ISA PnP (16 CDB)
26 - ABP5142 - Bus-Master ISA PnP with floppy (16 CDB)
27 - ABP902/3902 - Bus-Master PCI (16 CDB)
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| D | ChangeLog.sym53c8xx | 1 Sat May 12 12:00 2001 Gerard Roudier (groudier@club-internet.fr)
2 * version sym53c8xx-1.7.3c
3 - Ensure LEDC bit in GPCNTL is cleared when reading the NVRAM.
4 Fix sent by Stig Telfer <stig@api-networks.com>.
5 - Backport from SYM-2 the work-around that allows to support
6 hardwares that fail PCI parity checking.
7 - Check that we received at least 8 bytes of INQUIRY response
9 - Define scsi_set_pci_device() as nil for kernel < 2.4.4.
10 - + A couple of minor changes.
12 Sat Apr 7 19:30 2001 Gerard Roudier (groudier@club-internet.fr)
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| /Documentation/power/ |
| D | pci.rst | 2 PCI Power Management
7 An overview of concepts and the Linux kernel's interfaces related to PCI power
8 management. Based on previous work by Patrick Mochel <mochel@transmeta.com>
11 This document only covers the aspects of power management specific to PCI
13 power management refer to Documentation/driver-api/pm/devices.rst and
18 1. Hardware and Platform Support for PCI Power Management
19 2. PCI Subsystem and Device Power Management
20 3. PCI Device Drivers and Power Management
24 1. Hardware and Platform Support for PCI Power Management
27 1.1. Native and Platform-Based Power Management
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| /Documentation/driver-api/ |
| D | men-chameleon-bus.rst | 31 ----------------------
35 based devices.
38 -----------------------------------------
40 The current implementation is limited to PCI and PCIe based carrier devices
41 that only use a single memory resource and share the PCI legacy IRQ. Not
44 - Multi-resource MCB devices like the VME Controller or M-Module carrier.
45 - MCB devices that need another MCB device, like SRAM for a DMA Controller's
47 - A per-carrier IRQ domain for carrier devices that have one (or more) IRQs
48 per MCB device like PCIe based carriers with MSI or MSI-X support.
55 - The MEN Chameleon Bus itself,
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| D | sm501.rst | 12 The device may be connected by PCI or local bus with varying functions enabled.
15 ----
22 The core registers drivers for both PCI and generic bus based
29 The core re-uses the platform device system as the platform device
31 need to create a new bus-type and the associated code to go with it.
35 ---------
43 as this is by-far the most resource-sensitive of the on-chip functions.
59 -------------
66 The PCI driver assumes that the PCI card behaves as per the Silicon
69 There is an errata (AB-5) affecting the selection of the
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| /Documentation/devicetree/bindings/arm/ |
| D | arm,integrator.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
14 They are ARMv4, ARMv5 and ARMv6-capable using different core tiles,
23 - description: ARM Integrator Application Platform, this board has a PCI
24 host and several PCI slots, as well as a number of slots for logical
28 pre-packaged in a PC Tower form factor called Integrator/PP1 or a
31 - const: arm,integrator-ap
32 - description: ARM Integrator Compact Platform (HBI-0086), this board has
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| /Documentation/driver-api/gpio/ |
| D | bt8xxgpio.rst | 2 A driver for a selfmade cheap BT8xx based PCI GPIO-card (bt8xxgpio)
7 A generic digital 24-port PCI GPIO card can be built out of an ordinary
8 Brooktree bt848, bt849, bt878 or bt879 based analog TV tuner card. The
9 Brooktree chip is used in old analog Hauppauge WinTV PCI cards. You can easily
20 and put it on a custom PCI board, or one might only unsolder each individual
25 The GPIO pins are marked with G00-G23::
31 ---------------------------------------------------------------------------
32 --| ^ ^ |--
33 --| pin 86 pin 67 |--
34 --| |--
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| /Documentation/driver-api/acpi/ |
| D | scan_handlers.rst | 1 .. SPDX-License-Identifier: GPL-2.0
12 During system initialization and ACPI-based device hot-add, the ACPI namespace
23 During ACPI-based device hot-remove device nodes representing pieces of hardware
30 been registered. For example, if the given device node represents a PCI host
31 bridge, its registration should cause the PCI bus under that bridge to be
32 enumerated and PCI devices on that bus to be registered with the driver core.
33 Similarly, if the device node represents a PCI interrupt link, it is necessary
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