Searched +full:pcie +full:- +full:attached (Results 1 – 25 of 29) sorted by relevance
12
| /Documentation/PCI/ |
| D | pcieaer-howto.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 :Authors: - T. Long Nguyen <tom.l.nguyen@intel.com>
9 - Yanmin Zhang <yanmin.zhang@intel.com>
17 ----------------
19 This guide describes the basics of the PCI Express (PCIe) Advanced Error
22 the PCIe AER driver.
25 What is the PCIe AER Driver?
26 ----------------------------
28 PCIe error signaling can occur on the PCIe link itself
29 or on behalf of transactions initiated on the link. PCIe
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| /Documentation/devicetree/bindings/pci/ |
| D | baikal,bt1-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/baikal,bt1-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Baikal-T1 PCIe Root Port Controller
10 - Serge Semin <fancer.lancer@gmail.com>
13 Embedded into Baikal-T1 SoC Root Complex controller with a single port
14 activated. It's based on the DWC RC PCIe v4.60a IP-core, which is configured
18 performed by software. There four in- and four outbound iATU regions
19 which can be used to emit all required TLP types on the PCIe bus.
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| D | starfive,jh7110-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/starfive,jh7110-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 PCIe host controller
10 - Kevin Xie <kevin.xie@starfivetech.com>
13 - $ref: plda,xpressrich3-axi-common.yaml#
17 const: starfive,jh7110-pcie
21 - description: NOC bus clock
22 - description: Transport layer clock
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| D | snps,dw-pcie-ep.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare PCIe endpoint interface
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
14 Synopsys DesignWare PCIe host controller endpoint
16 # Please create a separate DT-schema for your DWC PCIe Endpoint controller
17 # and make sure it's assigned with the vendor-specific compatible string.
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| D | snps,dw-pcie.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare PCIe interface
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
14 Synopsys DesignWare PCIe host controller
16 # Please create a separate DT-schema for your DWC PCIe Root Port controller
17 # and make sure it's assigned with the vendor-specific compatible string.
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| D | snps,dw-pcie-common.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DWC PCIe RP/EP controller
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
14 Generic Synopsys DesignWare PCIe Root Port and Endpoint controller
22 DWC PCIe CSR space is normally accessed over the dedicated Data Bus
23 Interface - DBI. In accordance with the reference manual the register
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| /Documentation/devicetree/bindings/arm/bcm/ |
| D | brcm,hr2.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 A9 ARM CPUs, DDR2/DDR3 memory, PCIe GEN-2, USB 2.0 and USB 3.0, serial and NAND
13 flash and a PCIe attached integrated switching engine.
16 - Florian Fainelli <f.fainelli@gmail.com>
23 - enum:
24 - ubnt,unifi-switch8
25 - const: brcm,bcm53342
26 - const: brcm,hr2
|
| /Documentation/devicetree/bindings/phy/ |
| D | phy-miphy365x.txt | 5 for SATA and PCIe.
8 - compatible : Should be "st,miphy365x-phy"
9 - st,syscfg : Phandle / integer array property. Phandle of sysconfig group
11 an entry for each port sub-node, specifying the control
14 Required nodes : A sub-node is required for each channel the controller
16 'reg' and 'reg-names' properties are used inside these
21 - #phy-cells : Should be 1 (See second example)
23 - PHY_TYPE_SATA
24 - PHY_TYPE_PCI
25 - reg : Address and length of register sets for each device in
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| /Documentation/devicetree/bindings/net/bluetooth/ |
| D | brcm,bcm4377-bluetooth.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/bluetooth/brcm,bcm4377-bluetooth.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom BCM4377 family PCIe Bluetooth Chips
10 - Sven Peter <sven@svenpeter.dev>
13 This binding describes Broadcom BCM4377 family PCIe-attached bluetooth chips
14 usually found in Apple machines. The Wi-Fi part of the chip is described in
15 bindings/net/wireless/brcm,bcm4329-fmac.yaml.
18 - $ref: bluetooth-controller.yaml#
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| /Documentation/PCI/endpoint/ |
| D | pci-ntb-howto.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 PCI Non-Transparent Bridge (NTB) Endpoint Function (EPF) User Guide
9 This document is a guide to help users use pci-epf-ntb function driver
13 Documentation/PCI/endpoint/pci-ntb-function.rst
19 ---------------------------
27 2900000.pcie-ep 2910000.pcie-ep
32 2900000.pcie-ep 2910000.pcie-ep
36 -------------------------
40 # ls /sys/bus/pci-epf/drivers
49 Creating pci-epf-ntb Device
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| /Documentation/driver-api/ |
| D | men-chameleon-bus.rst | 31 ----------------------
38 -----------------------------------------
40 The current implementation is limited to PCI and PCIe based carrier devices
44 - Multi-resource MCB devices like the VME Controller or M-Module carrier.
45 - MCB devices that need another MCB device, like SRAM for a DMA Controller's
47 - A per-carrier IRQ domain for carrier devices that have one (or more) IRQs
48 per MCB device like PCIe based carriers with MSI or MSI-X support.
55 - The MEN Chameleon Bus itself,
56 - drivers for MCB Carrier Devices and
57 - the parser for the Chameleon table.
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| D | xillybus.rst | 10 - Introduction
11 -- Background
12 -- Xillybus Overview
14 - Usage
15 -- User interface
16 -- Synchronization
17 -- Seekable pipes
19 - Internals
20 -- Source code organization
21 -- Pipe attributes
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| D | device_link.rst | 57 device ``->probe`` callback or a boot-time PCI quirk.
61 ``->probe`` callback while the supplier hasn't started to probe yet: Had the
65 non-presence. [Note that it is valid to create a link from the consumer's
66 ``->probe`` callback while the supplier is still probing, but the consumer must
72 is added in the ``->probe`` callback of the supplier or consumer driver, it is
73 typically deleted in its ``->remove`` callback for symmetry. That way, if the
87 link is added from the consumer's ``->probe`` callback: ``DL_FLAG_RPM_ACTIVE``
93 Similarly, when the device link is added from supplier's ``->probe`` callback,
125 :c:func:`device_link_add()` may cause the PM-runtime usage counter of the
129 called twice in a row for the same consumer-supplier pair without removing the
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| /Documentation/networking/ |
| D | representors.rst | 1 .. SPDX-License-Identifier: GPL-2.0
9 used to control internal switching on SmartNICs. For the closely-related port
10 representors on physical (multi-port) switches, see
14 ----------
16 Since the mid-2010s, network cards have started offering more complex
17 virtualisation capabilities than the legacy SR-IOV approach (with its simple
18 MAC/VLAN-based switching model) can support. This led to a desire to offload
19 software-defined networks (such as OpenVSwitch) to these NICs to specify the
24 virtual switches and IOV devices. Just as each physical port of a Linux-
42 -----------
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| /Documentation/devicetree/bindings/bus/ |
| D | brcm,bus-axi.txt | 5 - compatible : brcm,bus-axi
7 - reg : iomem address range of chipcommon core
13 them manually through device tree. Use an interrupt-map to specify the
17 The top-level axi bus may contain children representing attached cores
25 compatible = "brcm,bus-axi";
28 #address-cells = <1>;
29 #size-cells = <1>;
30 #interrupt-cells = <1>;
31 interrupt-map-mask = <0x000fffff 0xffff>;
32 interrupt-map =
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| /Documentation/ABI/testing/ |
| D | sysfs-bus-pci | 4 Contact: linux-pci@vger.kernel.org
15 (Note: kernels before 2.6.28 may require echo -n).
20 Contact: linux-pci@vger.kernel.org
31 (Note: kernels before 2.6.28 may require echo -n).
36 Contact: linux-pci@vger.kernel.org
55 Contact: Chris Wright <chrisw@sous-sol.org>
72 Contact: Linux PCI developers <linux-pci@vger.kernel.org>
74 Writing a non-zero value to this attribute will
76 re-discover previously removed devices.
80 Contact: Linux PCI developers <linux-pci@vger.kernel.org>
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| D | sysfs-class-rapidio | 3 On-chip RapidIO controllers and PCIe-to-RapidIO bridges
21 0 = small (8-bit destination ID, max. 256 devices),
23 1 = large (16-bit destination ID, max. 65536 devices).
44 devices attached to it::
46 [rio@rapidio ~]$ ls /sys/class/rapidio_port/rapidio0/ -l
48 drwxr-xr-x 3 root root 0 Feb 11 15:10 00:e:0001
49 drwxr-xr-x 3 root root 0 Feb 11 15:10 00:e:0004
50 drwxr-xr-x 3 root root 0 Feb 11 15:10 00:e:0007
51 drwxr-xr-x 3 root root 0 Feb 11 15:10 00:s:0002
52 drwxr-xr-x 3 root root 0 Feb 11 15:10 00:s:0003
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| D | sysfs-class-cxl | 11 Contact: linuxppc-dev@lists.ozlabs.org
22 Contact: linuxppc-dev@lists.ozlabs.org
29 Users: https://github.com/ibm-capi/libcxl
33 Contact: linuxppc-dev@lists.ozlabs.org
39 Users: https://github.com/ibm-capi/libcxl
43 Contact: linuxppc-dev@lists.ozlabs.org
47 Users: https://github.com/ibm-capi/libcxl
51 Contact: linuxppc-dev@lists.ozlabs.org
55 Users: https://github.com/ibm-capi/libcxl
59 Contact: linuxppc-dev@lists.ozlabs.org
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| /Documentation/devicetree/bindings/net/dsa/ |
| D | mscc,ocelot.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vladimir Oltean <vladimir.oltean@nxp.com>
11 - Claudiu Manoil <claudiu.manoil@nxp.com>
12 - Alexandre Belloni <alexandre.belloni@bootlin.com>
13 - UNGLinuxDriver@microchip.com
16 There are multiple switches which are either part of the Ocelot-1 family, or
19 SPI or PCIe. The present DSA binding shall be used when the host controlling
21 (which is attached to an Ethernet port of the host), rather than through
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| /Documentation/accel/qaic/ |
| D | qaic.rst | 1 .. SPDX-License-Identifier: GPL-2.0-only
14 --------------------
21 non-empty and generate MSIs at a rate equivalent to the speed of the
42 ---------------
45 (circa 2023). Between hypervisors masking the PCIe MSI capability structure to
72 QAIC handles and enforces the required little endianness and 64-bit alignment,
96 QAIC creates an accel device per physical PCIe device. This accel device exists
97 for as long as the PCIe device is known to Linux.
99 The PCIe device may not be in the state to accept requests from userspace at
128 call is non-blocking. Success only indicates that the BOs have been queued
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| /Documentation/hwmon/ |
| D | corsair-psu.rst | 1 .. SPDX-License-Identifier: GPL-2.0-or-later
3 Kernel driver corsair-psu
37 -----------
41 These power supplies provide access to a micro-controller with 2 attached
43 power usage and 4 sensors for current levels and additional non-sensor information
47 -------------
81 -----------
83 It is an USB HID device, so it is auto-detected, supports hot-swapping and
93 ---------------
96 ocpmode Single or multi rail mode of the PCIe power connectors
|
| /Documentation/networking/device_drivers/ethernet/marvell/ |
| D | octeontx2.rst | 1 .. SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
12 - `Overview`_
13 - `Drivers`_
14 - `Basic packet flow`_
15 - `Devlink health reporters`_
16 - `Quality of service`_
23 PCI-compatible physical and virtual functions. Each functional block
25 RVU supports multiple PCIe SRIOV physical functions (PFs) and virtual
31 - Network pool or buffer allocator (NPA)
32 - Network interface controller (NIX)
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| /Documentation/fpga/ |
| D | dfl.rst | 7 - Enno Luebbers <enno.luebbers@intel.com>
8 - Xiao Guangrong <guangrong.xiao@linux.intel.com>
9 - Wu Hao <hao.wu@intel.com>
10 - Xu Yilun <yilun.xu@intel.com>
29 +----------+ +-->+----------+ +-->+----------+ +-->+----------+
32 +----------+ | | Feature | | | Feature | | | Feature |
33 | Next_DFH |--+ +----------+ | +----------+ | +----------+
34 +----------+ | Next_DFH |--+ | Next_DFH |--+ | Next_DFH |--> NULL
35 | ID | +----------+ +----------+ +----------+
36 +----------+ | ID | | ID | | ID |
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| /Documentation/arch/powerpc/ |
| D | cxl.rst | 28 +----------+ +---------+
34 +----------+ +---------+
36 | +------+ | PSL |
37 | | CAPP |<------>| |
38 +---+------+ PCIE +---------+
40 The POWER8/9 chip has a Coherently Attached Processor Proxy (CAPP)
41 unit which is part of the PCIe Host Bridge (PHB). This is managed
45 The FPGA (or coherently attached device) consists of two parts.
65 - POWER8 and PSL Version 8 are compliant to the CAIA Version 1.0.
66 - POWER9 and PSL Version 9 are compliant to the CAIA Version 2.0.
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| D | cxlflash.rst | 9 Accelerator Power Interface), which is available to certain PCIe slots
11 protocol through PCIe that allow PCIe adapters to look like special
12 purpose co-processors which can read or write an application's
40 - Any flash device (LUN) can be configured to be accessed as a
43 - Any flash device (LUN) can be configured to be accessed from
47 or physical LUN access) or access to a kernel/AFU-mediated
67 +-------------------------------+
71 +-------------------------------+
75 +-------------------------------+
78 +-------------------------------+
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