| /Documentation/devicetree/bindings/pci/ |
| D | fsl,imx6q-pcie-common.yaml | 4 $id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie-common.yaml#
7 title: Freescale i.MX6 PCIe RC/EP controller
14 Generic Freescale i.MX PCIe Root Port and Endpoint controller
29 fsl,imx7d-pcie-phy:
31 description: A phandle to an fsl,imx7d-pcie-phy node. Additional
32 required properties for imx7d-pcie, imx7d-pcie-ep, imx8mq-pcie,
33 and imx8mq-pcie-ep.
39 imx6sx-pcie, imx6sx-pcie-ep, to PCIE_PHY power domain for
40 imx7d-pcie, imx7d-pcie-ep, imx8mq-pcie and imx8mq-pcie-ep.
42 for imx6sx-pcie and imx6sx-pcie-ep.
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| D | fsl,imx6q-pcie.yaml | 4 $id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie.yaml#
7 title: Freescale i.MX6 PCIe host controller
14 This PCIe host controller is based on the Synopsys DesignWare PCIe IP
15 and thus inherits all the common properties defined in snps,dw-pcie.yaml.
19 See fsl,imx6q-pcie-ep.yaml for details on the Endpoint mode device tree
25 - fsl,imx6q-pcie
26 - fsl,imx6sx-pcie
27 - fsl,imx6qp-pcie
28 - fsl,imx7d-pcie
29 - fsl,imx8mq-pcie
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| D | fsl,imx6q-pcie-ep.yaml | 4 $id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie-ep.yaml#
7 title: Freescale i.MX6 PCIe Endpoint controller
14 This PCIe controller is based on the Synopsys DesignWare PCIe IP and
15 thus inherits all the common properties defined in snps,dw-pcie-ep.yaml.
22 - fsl,imx8mm-pcie-ep
23 - fsl,imx8mq-pcie-ep
24 - fsl,imx8mp-pcie-ep
25 - fsl,imx95-pcie-ep
30 - description: PCIe bridge clock.
31 - description: PCIe bus clock.
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| D | rcar-pci-host.yaml | 8 title: Renesas R-Car PCIe Host
20 - const: renesas,pcie-r8a7779 # R-Car H1
23 - renesas,pcie-r8a7742 # RZ/G1H
24 - renesas,pcie-r8a7743 # RZ/G1M
25 - renesas,pcie-r8a7744 # RZ/G1N
26 - renesas,pcie-r8a7790 # R-Car H2
27 - renesas,pcie-r8a7791 # R-Car M2-W
28 - renesas,pcie-r8a7793 # R-Car M2-N
29 - const: renesas,pcie-rcar-gen2 # R-Car Gen2 and RZ/G1
32 - renesas,pcie-r8a774a1 # RZ/G2M
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| D | qcom,pcie-ep.yaml | 4 $id: http://devicetree.org/schemas/pci/qcom,pcie-ep.yaml#
7 title: Qualcomm PCIe Endpoint Controller
16 - qcom,sa8775p-pcie-ep
17 - qcom,sdx55-pcie-ep
18 - qcom,sm8450-pcie-ep
20 - const: qcom,sdx65-pcie-ep
21 - const: qcom,sdx55-pcie-ep
27 - description: DesignWare PCIe registers
67 - description: PCIe Global interrupt
68 - description: PCIe Doorbell interrupt
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| D | qcom,pcie.yaml | 4 $id: http://devicetree.org/schemas/pci/qcom,pcie.yaml#
14 Qualcomm PCIe root complex controller is based on the Synopsys DesignWare
15 PCIe IP.
21 - qcom,pcie-apq8064
22 - qcom,pcie-apq8084
23 - qcom,pcie-ipq4019
24 - qcom,pcie-ipq6018
25 - qcom,pcie-ipq8064
26 - qcom,pcie-ipq8064-v2
27 - qcom,pcie-ipq8074
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| D | axis,artpec6-pcie.txt | 1 * Axis ARTPEC-6 PCIe interface
3 This PCIe host controller is based on the Synopsys DesignWare PCIe IP
4 and thus inherits all the common properties defined in snps,dw-pcie.yaml.
7 - compatible: "axis,artpec6-pcie", "snps,dw-pcie" for ARTPEC-6 in RC mode;
8 "axis,artpec6-pcie-ep", "snps,dw-pcie" for ARTPEC-6 in EP mode;
9 "axis,artpec7-pcie", "snps,dw-pcie" for ARTPEC-7 in RC mode;
10 "axis,artpec7-pcie-ep", "snps,dw-pcie" for ARTPEC-7 in EP mode;
11 - reg: base addresses and lengths of the PCIe controller (DBI),
21 - axis,syscon-pcie: A phandle pointing to the ARTPEC-6 system controller,
26 pcie@f8050000 {
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| D | ti,j721e-pci-ep.yaml | 8 title: TI J721E PCI EP (PCIe Wrapper)
16 - const: ti,j721e-pcie-ep
17 - const: ti,j784s4-pcie-ep
18 - description: PCIe EP controller in AM64
20 - const: ti,am64-pcie-ep
21 - const: ti,j721e-pcie-ep
22 - description: PCIe EP controller in J7200
24 - const: ti,j7200-pcie-ep
25 - const: ti,j721e-pcie-ep
37 ti,syscon-pcie-ctrl:
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| D | fsl,layerscape-pcie.yaml | 4 $id: http://devicetree.org/schemas/pci/fsl,layerscape-pcie.yaml#
7 title: Freescale Layerscape PCIe Root Complex(RC) controller
13 This PCIe RC controller is based on the Synopsys DesignWare PCIe IP
19 register available in the Freescale PCIe controller register set,
20 which can allow determining the underlying DesignWare PCIe controller version
27 - fsl,ls1012a-pcie
28 - fsl,ls1021a-pcie
29 - fsl,ls1028a-pcie
30 - fsl,ls1043a-pcie
31 - fsl,ls1046a-pcie
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| D | fsl,layerscape-pcie-ep.yaml | 4 $id: http://devicetree.org/schemas/pci/fsl,layerscape-pcie-ep.yaml#
7 title: Freescale Layerscape PCIe Endpoint(EP) controller
13 This PCIe EP controller is based on the Synopsys DesignWare PCIe IP.
19 register available in the Freescale PCIe controller register set,
20 which can allow determining the underlying DesignWare PCIe controller version
26 - fsl,ls2088a-pcie-ep
27 - fsl,ls1088a-pcie-ep
28 - fsl,ls1046a-pcie-ep
29 - fsl,ls1028a-pcie-ep
30 - fsl,lx2160ar2-pcie-ep
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| D | amlogic,axg-pcie.yaml | 4 $id: http://devicetree.org/schemas/pci/amlogic,axg-pcie.yaml#
7 title: Amlogic Meson AXG DWC PCIe SoC controller
13 Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core.
17 - $ref: /schemas/pci/snps,dw-pcie-common.yaml#
19 # We need a select here so we don't match all nodes with 'snps,dw-pcie'
24 - amlogic,axg-pcie
25 - amlogic,g12a-pcie
33 - amlogic,axg-pcie
34 - amlogic,g12a-pcie
35 - const: snps,dw-pcie
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| D | brcm,iproc-pcie.yaml | 4 $id: http://devicetree.org/schemas/pci/brcm,iproc-pcie.yaml#
7 title: Broadcom iProc PCIe controller with the platform bus interface
22 - brcm,iproc-pcie
25 - brcm,iproc-pcie-paxb-v2
27 - brcm,iproc-pcie-paxc
29 - brcm,iproc-pcie-paxc-v2
34 Base address and length of the PCIe controller I/O register space
47 - const: pcie-phy
51 brcm,pcie-ob:
57 brcm,pcie-ob-axi-offset:
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| D | ti,j721e-pci-host.yaml | 8 title: TI J721E PCI Host (PCIe Wrapper)
16 - const: ti,j721e-pcie-host
17 - const: ti,j784s4-pcie-host
18 - description: PCIe controller in AM64
20 - const: ti,am64-pcie-host
21 - const: ti,j721e-pcie-host
22 - description: PCIe controller in J7200
24 - const: ti,j7200-pcie-host
25 - const: ti,j721e-pcie-host
26 - description: PCIe controller in J722S
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| D | samsung,exynos-pcie.yaml | 4 $id: http://devicetree.org/schemas/pci/samsung,exynos-pcie.yaml#
7 title: Samsung SoC series PCIe Host Controller
14 Exynos5433 SoC PCIe host controller is based on the Synopsys DesignWare
15 PCIe IP and thus inherits all the common properties defined in
16 snps,dw-pcie.yaml.
19 - $ref: /schemas/pci/snps,dw-pcie.yaml#
23 const: samsung,exynos5433-pcie
29 - description: PCIe configuration space region.
42 - description: PCIe bridge clock
43 - description: PCIe bus clock
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| D | aardvark-pci.txt | 1 Aardvark PCIe controller
3 This PCIe controller is used on the Marvell Armada 3700 ARM64 SoC.
5 The Device Tree node describing an Aardvark PCIe controller must
8 - compatible: Should be "marvell,armada-3700-pcie"
9 - reg: range of registers for the PCIe controller
10 - interrupts: the interrupt line of the PCIe controller
16 - msi-controller: indicates that the PCIe controller can itself
20 define the mapping of the PCIe interface to interrupt numbers.
22 - phys: the PCIe PHY handle
26 In addition, the Device Tree describing an Aardvark PCIe controller
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| D | ti-pci.txt | 3 PCIe DesignWare Controller
4 - compatible: Should be "ti,dra7-pcie" for RC (deprecated)
5 Should be "ti,dra7-pcie-ep" for EP (deprecated)
6 Should be "ti,dra746-pcie-rc" for dra74x/dra76 in RC mode
7 Should be "ti,dra746-pcie-ep" for dra74x/dra76 in EP mode
8 Should be "ti,dra726-pcie-rc" for dra72x in RC mode
9 Should be "ti,dra726-pcie-ep" for dra72x in EP mode
11 - phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
13 - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",
14 where <X> is the instance number of the pcie from the HW spec.
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| D | brcm,stb-pcie.yaml | 4 $id: http://devicetree.org/schemas/pci/brcm,stb-pcie.yaml#
7 title: Brcmstb PCIe Host Controller
16 - brcm,bcm2711-pcie # The Raspberry Pi 4
17 - brcm,bcm4908-pcie
18 - brcm,bcm7211-pcie # Broadcom STB version of RPi4
19 - brcm,bcm7216-pcie # Broadcom 7216 Arm
20 - brcm,bcm7278-pcie # Broadcom 7278 Arm
21 - brcm,bcm7425-pcie # Broadcom 7425 MIPs
22 - brcm,bcm7435-pcie # Broadcom 7435 MIPs
23 - brcm,bcm7445-pcie # Broadcom 7445 Arm
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| D | pcie-al.txt | 1 * Amazon Annapurna Labs PCIe host bridge
3 Amazon's Annapurna Labs PCIe Host Controller is based on the Synopsys DesignWare
5 Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
13 - "amazon,al-alpine-v2-pcie" for alpine_v2
14 - "amazon,al-alpine-v3-pcie" for alpine_v3
25 - "config" PCIe ECAM space
27 - "dbi" Designware PCIe registers
31 pcie-external0: pcie@fb600000 {
32 compatible = "amazon,al-alpine-v3-pcie";
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| D | mediatek-pcie.txt | 1 MediaTek Gen2 PCIe controller
5 "mediatek,mt2701-pcie"
6 "mediatek,mt2712-pcie"
7 "mediatek,mt7622-pcie"
8 "mediatek,mt7623-pcie"
9 "mediatek,mt7629-pcie"
10 "airoha,en7523-pcie"
22 - free_ck :for reference clock of PCIe subsys
34 - phy-names : Must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
48 - reset-names: Must be "pcie-rst0", "pcie-rst1", "pcie-rstN".. based on the
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| /Documentation/devicetree/bindings/phy/ |
| D | qcom,sc8280xp-qmp-pcie-phy.yaml | 4 $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-pcie-phy.yaml#
7 title: Qualcomm QMP PHY controller (PCIe, SC8280XP)
14 controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
19 - qcom,sa8775p-qmp-gen4x2-pcie-phy
20 - qcom,sa8775p-qmp-gen4x4-pcie-phy
21 - qcom,sc8180x-qmp-pcie-phy
22 - qcom,sc8280xp-qmp-gen3x1-pcie-phy
23 - qcom,sc8280xp-qmp-gen3x2-pcie-phy
24 - qcom,sc8280xp-qmp-gen3x4-pcie-phy
25 - qcom,sdm845-qhp-pcie-phy
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| D | brcm,cygnus-pcie-phy.yaml | 4 $id: http://devicetree.org/schemas/phy/brcm,cygnus-pcie-phy.yaml#
7 title: Broadcom Cygnus PCIe PHY
15 pattern: "^pcie[-|_]phy(@.*)?$"
19 - const: brcm,cygnus-pcie-phy
24 Base address and length of the PCIe PHY block
33 "^pcie-phy@[0-9]+$":
37 PCIe PHY child nodes
43 The PCIe PHY port number
63 compatible = "brcm,cygnus-pcie-phy";
68 pcie0_phy: pcie-phy@0 {
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| D | hisilicon,phy-hi3670-pcie.yaml | 4 $id: http://devicetree.org/schemas/phy/hisilicon,phy-hi3670-pcie.yaml#
7 title: HiSilicon Kirin970 PCIe PHY
13 Bindings for PCIe PHY on HiSilicon Kirin 970.
17 const: hisilicon,hi970-pcie-phy
27 description: The PCIe PHY power supply
31 - description: PCIe PHY clock
32 - description: PCIe AUX clock
33 - description: PCIe APB PHY clock
34 - description: PCIe APB SYS clock
35 - description: PCIe ACLK clock
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| D | airoha,en7581-pcie-phy.yaml | 4 $id: http://devicetree.org/schemas/phy/airoha,en7581-pcie-phy.yaml#
13 The PCIe PHY supports physical layer functionality for PCIe Gen2/Gen3 port.
17 const: airoha,en7581-pcie-phy
21 - description: PCIE analog base address
22 - description: PCIE lane0 base address
23 - description: PCIE lane1 base address
24 - description: PCIE lane0 detection time base address
25 - description: PCIE lane1 detection time base address
26 - description: PCIE Rx AEQ base address
57 compatible = "airoha,en7581-pcie-phy";
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| /Documentation/ABI/testing/ |
| D | sysfs-driver-xdata | 1 What: /sys/class/misc/drivers/dw-xdata-pcie.<device>/write
5 Description: Allows the user to enable the PCIe traffic generator which
7 Endpoint direction or to disable the PCIe traffic generator
13 echo 1 > /sys/class/misc/dw-xdata-pcie.<device>/write
15 echo 0 > /sys/class/misc/dw-xdata-pcie.<device>/write
17 The user can read the current PCIe link throughput generated
21 cat /sys/class/misc/dw-xdata-pcie.<device>/write
26 What: /sys/class/misc/dw-xdata-pcie.<device>/read
30 Description: Allows the user to enable the PCIe traffic generator which
32 Complex direction or to disable the PCIe traffic generator
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| /Documentation/PCI/ |
| D | pcieaer-howto.rst | 19 This guide describes the basics of the PCI Express (PCIe) Advanced Error
22 the PCIe AER driver.
25 What is the PCIe AER Driver?
28 PCIe error signaling can occur on the PCIe link itself
29 or on behalf of transactions initiated on the link. PCIe
32 required of all PCIe components providing a minimum defined
34 capability is implemented with a PCIe Advanced Error Reporting
37 The PCIe AER driver provides the infrastructure to support PCIe Advanced
38 Error Reporting capability. The PCIe AER driver provides three basic
45 The AER driver only attaches to Root Ports and RCECs that support the PCIe
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