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/Documentation/devicetree/bindings/phy/
Dqcom,pcie2-phy.yaml4 $id: http://devicetree.org/schemas/phy/qcom,pcie2-phy.yaml#
7 title: Qualcomm PCIe2 PHY controller
13 The Qualcomm PCIe2 PHY is a Synopsys based phy found in a number of Qualcomm
19 - const: qcom,qcs404-pcie2-phy
20 - const: qcom,pcie2-phy
71 compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy";
Dtransmit-amplitude.yaml55 - pcie2
/Documentation/devicetree/bindings/pinctrl/
Dmarvell,armada-39x-pinctrl.txt31 mpp13 13 gpio, dev(ad15), pcie2(clkreq), led(data)
80 mpp58 58 gpio, i2c1(sck), pcie2(clkreq), spi1(miso), sd0(d1), ua1(rxd)
Dmarvell,armada-38x-pinctrl.txt31 … 13 gpio, ge0(rxd1), pcie0(clkreq), pcie1(clkreq) [1], spi0(cs2), dev(ad15), pcie2(clkreq)
76 mpp58 58 gpio, pcie1(clkreq) [1], i2c1(sck), pcie2(clkreq), spi1(miso), sd0(d1), ua1(…
Drealtek,rtd1619b-pinctrl.yaml60 pcie2, sd, sdio_loc0, sdio_loc1, hi, hi_m, dc_fan, pll_test_loc0, pll_test_loc1,
/Documentation/devicetree/bindings/arm/marvell/
Dcp110-system-controller.txt97 mpp6 6 gpio, dev(ad11), ge0(txd3), spi0(csn2), au(i2sextclk), sata1(present_act), pcie2(clkreq), ua…
119 mpp28 28 gpio, dev(csn1), spi1(csn0), mss_gpio5, ge0(rxd2), spi0(csn5), pcie2(clkreq), ptp(pulse), …
124 …io(pwr10), mss_spi(csn), tdm(fsync), au(i2smclk), sdio(bus_pwr), xg(mdio), pcie2(clkreq), mss_gpio1
127 … ptp(clk), synce1(clk), au(i2sbclk), sata0(present_act), xg(mdc), ge(mdc), pcie2(clkreq), mss_gpio5
/Documentation/admin-guide/perf/
Dnvidia-pmu.rst230 | |PCI R/W|Translated,|Translated | CPU | CPU/PCIE1| GPU/PCIE2|
248 PCIE2 traffic represents reads and relaxed ordered (RO) writes.
287 | | PCI R/W | CPU | CPU/PCIE1| PCIE2 |
299 PCIE2 traffic represents reads and relaxed ordered (RO) writes.
/Documentation/devicetree/bindings/pci/
Dsnps,dw-pcie-ep.yaml199 phy-names = "pcie0", "pcie1", "pcie2", "pcie3";