Home
last modified time | relevance | path

Searched full:pcs (Results 1 – 25 of 54) sorted by relevance

123

/Documentation/devicetree/bindings/net/pcs/
Dfsl,lynx-pcs.yaml4 $id: http://devicetree.org/schemas/net/pcs/fsl,lynx-pcs.yaml#
7 title: NXP Lynx PCS
13 NXP Lynx 10G and 28G SerDes have Ethernet PCS devices which can be used as
19 const: fsl,lynx-pcs
36 qsgmii_pcs1: ethernet-pcs@1 {
37 compatible = "fsl,lynx-pcs";
Dmediatek,sgmiisys.yaml4 $id: http://devicetree.org/schemas/net/pcs/mediatek,sgmiisys.yaml#
13 The MediaTek SGMIISYS controller provides a SGMII PCS and some clocks
45 pcs:
47 description: MediaTek LynxI HSGMII PCS
84 - pcs
88 pcs: false
Dsnps,dw-xpcs.yaml4 $id: http://devicetree.org/schemas/net/pcs/snps,dw-xpcs.yaml#
7 title: Synopsys DesignWare Ethernet PCS
16 controlled by means of the IEEE std. Clause 45 registers set. The PCS can be
21 The PCS CSRs can be accessible either over the Ethernet MDIO bus or directly
83 PCS/PMA layer can be clocked by an internal reference clock source
111 ethernet-pcs@1f05d000 {
128 ethernet-pcs@0 {
Drenesas,rzn1-miic.yaml4 $id: http://devicetree.org/schemas/net/pcs/renesas,rzn1-miic.yaml#
48 the values defined in dt-bindings/net/pcs-rzn1-miic.h.
67 one of the values defined in dt-bindings/net/pcs-rzn1-miic.h.
131 #include <dt-bindings/net/pcs-rzn1-miic.h>
/Documentation/devicetree/bindings/net/
Dnvidia,tegra234-mgbe.yaml49 - const: eee-pcs
50 - const: rx-pcs-input
51 - const: rx-pcs-m
52 - const: rx-pcs
53 - const: tx-pcs
61 - const: pcs
137 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
138 "rx-pcs", "tx-pcs";
141 reset-names = "mac", "pcs";
Dfsl,fman-dtsec.yaml101 description: See pcs-handle.
103 pcs-handle:
108 pcs-handle-names is absent, and phy-connection-type is "xgmii", then the first
109 reference will be assumed to be for "xfi". Otherwise, if pcs-handle-names is
112 pcs-handle-names:
120 description: The type of each PCS in pcsphy-handle.
124 description: A reference to the (TBI-based) PCS
133 pcs-handle-names:
134 - pcs-handle
166 pcs-handle = <&pcsphy4>, <&qsgmiib_pcs1>;
[all …]
Dfsl,fman-mdio.yaml41 Fman has internal MDIO for internal PCS(Physical
59 set when reading internal PCS registers. MDIO reads to
60 internal PCS registers may result in having the
64 PCS registers through MDIO. As a workaround, all internal
71 - For "fsl,fman-memac-mdio" compatible internal mdio bus, the PHY is PCS PHY.
72 The PCS PHY address should correspond to the value of the appropriate
Dfsl,qoriq-mc-dpmac.yaml27 pcs-handle:
30 A reference to a node representing a PCS PHY device found on
54 pcs-handle = <&pcs3_1>;
Drenesas,rzn1-gmac.yaml33 pcs-handle:
35 phandle pointing to a PCS sub-node compatible with
62 pcs-handle = <&mii_conv1>;
Dethernet-controller.yaml111 pcs-handle:
116 Specifies a reference to a node representing a PCS PHY device on a MDIO
119 pcs-handle-names:
121 The name of each PCS in pcs-handle.
262 pcs-handle-names: [pcs-handle]
Dxlnx,axi-ethernet.yaml101 - description: MGT reference clock (used by optional internal PCS/PMA PHY)
120 pcs-handle:
121 description: Phandle to the internal PCS/PMA PHY in SGMII or 1000Base-X
122 modes, where "pcs-handle" should be used to point to the PCS/PMA PHY,
Damd-xgbe.txt7 - PCS registers
15 The last interrupt listed should be the PCS auto-negotiation interrupt.
Daltr,tse.yaml108 - const: pcs
123 reg-names = "control_port", "rx_csr", "rx_desc", "rx_resp", "tx_csr", "tx_desc", "pcs";
/Documentation/networking/
Dsfp-phylink.rst219 should be used to configure the MAC when the MAC and PCS are not
249 10. Some Ethernet controllers work in pair with a PCS (Physical Coding Sublayer)
252 PCS whose operation is transparent, some other require dedicated PCS
254 provides a PCS abstraction through :c:type:`struct phylink_pcs <phylink_pcs>`.
256 Identify if your driver has one or more internal PCS blocks, and/or if
257 your controller can use an external PCS block that might be internally
260 If your controller doesn't have any internal PCS, you can go to step 11.
262 If your Ethernet controller contains one or several PCS blocks, create
263 one :c:type:`struct phylink_pcs <phylink_pcs>` instance per PCS block within
268 struct phylink_pcs pcs;
[all …]
/Documentation/devicetree/bindings/net/dsa/
Drenesas,rzn1-a5psw.yaml70 pcs-handle:
73 phandle pointing to a PCS sub-node compatible with
114 pcs-handle = <&mii_conv4>;
121 pcs-handle = <&mii_conv3>;
/Documentation/devicetree/bindings/phy/
Dti-phy.txt13 set PCS delay value.
58 - syscon-pcs : phandle/offset pair. Phandle to the system control module and the
59 register offset to write the PCS delay value.
Dmediatek,mt7988-xfi-tphy.yaml14 used by the (10G/5G) USXGMII PCS and (1G/2.5G) LynxI PCS found in
Dfsl,imx8mq-usb-phy.yaml70 fsl,phy-pcs-tx-deemph-3p5db-attenuation-db:
78 fsl,phy-pcs-tx-swing-full-percent:
Dtransmit-amplitude.yaml7 title: Common PHY and network PCS transmit amplitude property
/Documentation/networking/device_drivers/ethernet/freescale/dpaa2/
Dmac-phy-support.rst54 | MC firmware polling MAC PCS for link |
56 | | PCS | | PCS | | PCS | | PCS | |
65 the MC firmware by polling the MAC PCS. Without the need to register a
187 mode, the MC firmware does not access the PCS registers). One can check for
/Documentation/devicetree/bindings/pci/
Dsnps,dw-pcie-common.yaml90 Controller Core-PCS PIPE interface clock. It's normally
91 supplied by an external PCS-PHY.
159 - description: PIPE-interface (Core-PCS) logic reset
164 - description: PCS/PHY block reset
Dsnps,dw-pcie-ep.yaml85 PHY/PCS configuration registers. Some platforms can have the
86 PCS and PHY CSRs accessible over a dedicated memory mapped
/Documentation/devicetree/bindings/iio/light/
Drohm,bu27008.yaml17 LCD backlight of TVs, mobile phones and tablet PCs.
Drohm,bu27010.yaml18 and tablet PCs.
/Documentation/sound/soc/
Dpops-clicks.rst6 of components within the audio subsystem. This is noticeable on PCs when an

123