Searched full:pe (Results 1 – 25 of 26) sorted by relevance
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| /Documentation/arch/powerpc/ |
| D | pci_iov_resource_on_powernv.rst | 22 A Partitionable Endpoint (PE) is a way to group the various resources
28 There is thus, in HW, a table of PE states that contains a pair of "frozen"
30 cleared independently) for each PE.
32 When a PE is frozen, all stores in any direction are dropped and all loads
54 correspondence between a PCIe RID (bus/dev/fn) with a PE number.
57 - For DMA we then provide an entire address space for each PE that can
66 bridge being triggered. There's a PE# in the interrupt controller
67 descriptor table as well which is compared with the PE# obtained from
96 maps each segment to a PE#. That allows portions of the MMIO space
103 can be assigned to a PE.
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| /Documentation/arch/riscv/ |
| D | boot-image-header.rst | 22 u32 res3; /* Reserved for PE COFF offset */
24 This header format is compliant with PE/COFF header and largely inspired from
32 needs PE/COFF image header in the beginning of the kernel image in order to
35 PE/COFF header.
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| /Documentation/arch/loongarch/ |
| D | booting.rst | 30 Linux/LoongArch kernel images are EFI images. Being PE files, they have
42 u32 pe_header - _head /* Offset to the PE header */
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| /Documentation/driver-api/ |
| D | vfio.rst | 474 one table per a IOMMU group which is a Partitionable Endpoint (PE)
475 (PE is often a PCI domain but not always).
483 out of the window leads to the whole PE isolation.
492 4) According to sPAPR specification, A Partitionable Endpoint (PE) is an I/O
494 error recovery. A PE may be a single or multi-function IOA (IO Adapter), a
561 * PE, and put child devices belonging to same IOMMU group to the
562 * PE instance for later reference.
565 /* Check the PE's state and make sure it's in functional state */
588 * of the PCI device. Check the PE's state to see if that has been
594 * produce any more PCI traffic from/to the affected PE until
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| D | pps.rst | 229 12 PE * *
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| /Documentation/translations/zh_CN/arch/arm64/ |
| D | booting.txt | 102 u32 res5; /* 保留 （用于 PE COFF 偏移） */
112 res5 是到 PE 文件头的偏移，而 PE 文件头含有 EFI 的启动入口点
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| /Documentation/translations/zh_TW/arch/arm64/ |
| D | booting.txt | 106 u32 res5; /* 保留 （用於 PE COFF 偏移） */
116 res5 是到 PE 文件頭的偏移，而 PE 文件頭含有 EFI 的啓動入口點
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| /Documentation/admin-guide/ |
| D | efi-stub.rst | 6 as a PE/COFF image, thereby convincing EFI firmware loaders to load
17 masquerades as a PE/COFF image and the EFI stub is linked into the
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| /Documentation/translations/zh_CN/arch/riscv/ |
| D | boot-image-header.rst | 35 u32 res3; /* Reserved for PE COFF offset */
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| /Documentation/ABI/testing/ |
| D | sysfs-bus-coresight-devices-etm4x | 21 Description: (Read) Indicates the number of PE comparator inputs that are
94 What: /sys/bus/coresight/devices/etm<N>/pe
98 Description: (RW) Controls which PE to trace.
296 Description: (RW) Access the start stop control register for PE input
329 Description: (RW) Access the selected single show PE comparator control
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| /Documentation/translations/zh_CN/core-api/ |
| D | printk-formats.rst | 105 %pe -ENOSPC
233 %*pE[achnops]
241 %*pE "\eb \C\a"\220\r]"
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| /Documentation/arch/arm/ |
| D | uefi.rst | 34 PE/COFF executable, including a loader application that makes it possible to
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| /Documentation/core-api/ |
| D | printk-formats.rst | 101 %pe -ENOSPC
106 argument to %pe gets treated as ordinary %p.
251 %*pE[achnops]
260 %*pE "\eb \C\a"\220\r]"
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | nvidia,tegra210-pinmux.yaml | 88 i2s5a, i2s5b, iqc0, iqc1, jtag, pe, pe0, pe1, pmi, pwm0,
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| D | ingenic,pinctrl.yaml | 22 pins. The X2000 and the X2100 contains 5 GPIO ports, PA to PE, for a total of
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| D | nvidia,tegra124-pinmux.yaml | 112 pe0, pe, pe1, dp, rtck, sys, clk, tmds, csi, dsi_b ]
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| D | allwinner,sun4i-a10-pinctrl.yaml | 293 uart1_pe_pins: uart1-pe-pins {
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| /Documentation/arch/arm64/ |
| D | booting.rst | 86 u32 res5; /* reserved (used for PE COFF offset) */
96 res5 is an offset to the PE header and the PE header has the EFI
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| D | sme.rst | 452 * PSTATE.SM, if this is 1 then the PE is in streaming mode. When the value
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| /Documentation/devicetree/bindings/net/can/ |
| D | fsl,flexcan.yaml | 105 Select the clock source to the CAN Protocol Engine (PE). It's SoC
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| /Documentation/trace/coresight/ |
| D | coresight-etm4x-reference.rst | 280 Access a single shot PE comparator input control register.
311 Access PE start stop comparator input control registers
604 Number of PE comparator inputs
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| D | coresight.rst | 525 The kernel can be built to write the PID value into the PE ContextID registers.
526 For a kernel running at EL1, the PID is stored in CONTEXTIDR_EL1. A PE may
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| /Documentation/i2c/busses/ |
| D | i2c-i801.rst | 167 Here the host bridge ID is 2570 (82865G/PE/P), the subvendor ID is 1043
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| /Documentation/virt/kvm/devices/ |
| D | arm-vgic-its.rst | 182 - RDBase is the PE number (GICR_TYPER.Processor_Number semantic),
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| /Documentation/arch/x86/ |
| D | boot.rst | 1422 The boot loader MUST respect the kernel's PE/COFF metadata when it comes
1424 the size of the file itself, and any other aspect of the PE/COFF header
1425 that may affect correct operation of the image as a PE/COFF binary in the
1445 NOTE: The EFI Handover Protocol is deprecated in favour of the ordinary PE/COFF
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