Searched full:pl310 (Results 1 – 3 of 3) sorted by relevance
| /Documentation/devicetree/bindings/cache/ |
| D | l2c2x0.yaml | 14 PL220/PL310 and variants) based level 2 cache controller. All these various
34 - arm,pl310-cache
37 # DEPRECATED by "brcm,bcm11351-a2-pl310-cache"
38 - bcm,bcm11351-a2-pl310-cache
42 - brcm,bcm11351-a2-pl310-cache
53 # with arm,pl310-cache controller.
55 - const: arm,pl310-cache
109 I/O coherent mode. Valid only when the arm,pl310-cache compatible
157 description: The default behavior of the L220 or PL310 cache
166 description: enable parity checking on the L2 cache (L220 or PL310).
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | st,stih407-irq-syscfg.yaml | 14 Management), and PL310 L2 Cache IRQs are controlled using System
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| /Documentation/arch/arm/ |
| D | marvell.rst | 442 - Core: ARM Cortex-A9, PL310 L2CC
451 - Core: Quad Core ARM Cortex-A9, PL310 L2CC
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