| /Documentation/devicetree/bindings/clock/ |
| D | qca,ath79-pll.txt | 1 Binding for Qualcomm Atheros AR7xxx/AR9XXX PLL controller
6 - compatible: has to be "qca,<soctype>-pll" and one of the following
8 - "qca,ar7100-pll"
9 - "qca,ar7240-pll"
10 - "qca,ar9130-pll"
11 - "qca,ar9330-pll"
12 - "qca,ar9340-pll"
13 - "qca,qca9550-pll"
24 pll-controller@18050000 {
25 compatible = "qca,ar9132-pll", "qca,ar9130-pll";
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| D | keystone-pll.txt | 1 Binding for keystone PLLs. The main PLL IP typically has a multiplier,
2 a divider and a post divider. The additional PLL IPs like ARMPLL, DDRPLL
4 PLL is controlled by a PLL controller registers along with memory mapped
13 - compatible : shall be "ti,keystone,main-pll-clock" or "ti,keystone,pll-clock"
15 - reg - pll control0 and pll multiplier registers
17 post-divider registers are applicable only for main pll clock
24 compatible = "ti,keystone,main-pll-clock";
33 compatible = "ti,keystone,pll-clock";
35 clock-output-names = "pa-pll-clk";
42 - compatible : shall be "ti,keystone,pll-mux-clock"
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| D | vt8500.txt | 9 "via,vt8500-pll-clock" - for a VT8500/WM8505 PLL clock
10 "wm,wm8650-pll-clock" - for a WM8650 PLL clock
11 "wm,wm8750-pll-clock" - for a WM8750 PLL clock
12 "wm,wm8850-pll-clock" - for a WM8850 PLL clock
15 Required properties for PLL clocks:
16 - reg : shall be the control register offset from PMC base for the pll clock.
23 be a pll output.
61 compatible = "wm,wm8650-pll-clock";
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| D | silabs,si5351.yaml | 53 silabs,pll-source:
56 A list of cell pairs containing a PLL index and its source. Allows to
60 - description: PLL A (0) or PLL B (1)
62 - description: PLL source, XTAL (0) or CLKIN (1, Si5351C only).
65 silabs,pll-reset-mode:
69 description: A list of cell pairs containing a PLL index and its reset mode.
72 - description: PLL A (0) or PLL B (1)
75 Reset mode for the PLL. Mode can be one of:
77 0 - reset whenever PLL rate is adjusted (default mode)
78 1 - do not reset when PLL rate is adjusted
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| D | snps,hsdk-pll-clock.txt | 1 Binding for the HSDK Generic PLL clock
8 - compatible: should be "snps,hsdk-<name>-pll-clock"
9 "snps,hsdk-core-pll-clock"
10 "snps,hsdk-gp-pll-clock"
11 "snps,hsdk-hdmi-pll-clock"
13 - clocks: shall be the input parent clock phandle for the PLL.
24 compatible = "snps,hsdk-core-pll-clock";
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| D | sophgo,sg2042-pll.yaml | 4 $id: http://devicetree.org/schemas/clock/sophgo,sg2042-pll.yaml#
7 title: Sophgo SG2042 PLL Clock Generator
14 const: sophgo,sg2042-pll
21 - description: Oscillator(Clock Generation IC) for Main/Fixed PLL (25 MHz)
22 - description: Oscillator(Clock Generation IC) for DDR PLL 0 (25 MHz)
23 - description: Oscillator(Clock Generation IC) for DDR PLL 1 (25 MHz)
34 See <dt-bindings/clock/sophgo,sg2042-pll.h> for valid indices.
48 compatible = "sophgo,sg2042-pll";
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| D | qcom,mmcc.yaml | 83 - description: PLL 3 clock
84 - description: PLL 3 Vote clock
89 - description: HDMI phy PLL clock
149 - description: HDMI phy PLL clock
150 - description: eDP phy PLL link clock
151 - description: eDP phy PLL vco clock
188 - description: HDMI phy PLL clock
189 - description: eDP phy PLL link clock
190 - description: eDP phy PLL vco clock
232 - description: Global PLL 0 clock
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| D | snps,pll-clock.txt | 1 Binding for the AXS10X Generic PLL clock
8 - compatible: should be "snps,axs10x-<name>-pll-clock"
9 "snps,axs10x-arc-pll-clock"
10 "snps,axs10x-pgu-pll-clock"
11 - reg: should always contain 2 pairs address - length: first for PLL config
13 - clocks: shall be the input parent clock phandle for the PLL.
24 compatible = "snps,axs10x-arc-pll-clock";
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| D | fsl,qoriq-clock-legacy.yaml | 22 - fsl,qoriq-core-pll-1.0
23 - fsl,qoriq-core-pll-2.0
28 - fsl,qoriq-platform-pll-1.0
29 - fsl,qoriq-platform-pll-2.0
74 - fsl,qoriq-core-pll-1.0
75 - fsl,qoriq-core-pll-2.0
81 * 0 - equal to the PLL frequency
82 * 1 - equal to the PLL frequency divided by 2
83 * 2 - equal to the PLL frequency divided by 4
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| D | amlogic,c3-pll-clkc.yaml | 5 $id: http://devicetree.org/schemas/clock/amlogic,c3-pll-clkc.yaml#
8 title: Amlogic C3 series PLL Clock Controller
18 const: amlogic,c3-pll-clkc
25 - description: input top pll
26 - description: input mclk pll
27 - description: input fix pll
54 compatible = "amlogic,c3-pll-clkc";
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| D | amlogic,s4-peripherals-clkc.yaml | 23 - description: input fixed pll div2
24 - description: input fixed pll div2p5
25 - description: input fixed pll div3
26 - description: input fixed pll div4
27 - description: input fixed pll div5
28 - description: input fixed pll div7
29 - description: input hifi pll
30 - description: input gp0 pll
35 - description: input hdmi pll
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| D | axs10x-i2s-pll-clock.txt | 1 Binding for the AXS10X I2S PLL clock
8 - compatible: shall be "snps,axs10x-i2s-pll-clock"
9 - reg : address and length of the I2S PLL register set.
10 - clocks: shall be the input parent clock phandle for the PLL.
21 compatible = "snps,axs10x-i2s-pll-clock";
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| D | amlogic,a1-peripherals-clkc.yaml | 27 - description: input fixed pll div2
28 - description: input fixed pll div3
29 - description: input fixed pll div5
30 - description: input fixed pll div7
31 - description: input hifi pll
33 - description: input sys pll
58 #include <dt-bindings/clock/amlogic,a1-pll-clkc.h>
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| D | mediatek,mt7988-xfi-pll.yaml | 4 $id: http://devicetree.org/schemas/clock/mediatek,mt7988-xfi-pll.yaml#
7 title: MediaTek MT7988 XFI PLL Clock Controller
13 The MediaTek XFI PLL controller provides the 156.25MHz clock for the
18 const: mediatek,mt7988-xfi-pll
43 compatible = "mediatek,mt7988-xfi-pll";
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| D | starfive,jh7110-pll.yaml | 4 $id: http://devicetree.org/schemas/clock/starfive,jh7110-pll.yaml#
7 title: StarFive JH7110 PLL Clock Generator
11 Each PLL works in integer mode or fraction mode, with configuration
22 const: starfive,jh7110-pll
43 compatible = "starfive,jh7110-pll";
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| D | xgene.txt | 9 "apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock
10 "apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock
13 "apm,xgene-socpll-v2-clock" - for a X-Gene SoC PLL v2 clock
14 "apm,xgene-pcppll-v2-clock" - for a X-Gene PCP PLL v2 clock
16 Required properties for SoC or PCP PLL clocks:
17 - reg : shall be the physical PLL register address for the pll clock.
21 - clock-output-names : shall be the name of the PLL referenced by derive
23 Optional properties for PLL clocks:
24 - clock-names : shall be the name of the PLL. If missing, use the device name.
32 Optional properties for PLL clocks:
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| D | baikal,bt1-ccu-pll.yaml | 5 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-pll.yaml#
8 title: Baikal-T1 Clock Control Unit PLL
52 with an interface wrapper (so called safe PLL' clocks switcher) to simplify
53 the PLL configuration procedure. The PLLs work as depicted on the next
71 divider, NF - PLL clock multiplier, OD - VCO output clock divider, CLKOUT -
72 output clock, BWADJ is the PLL bandwidth adjustment parameter. At this moment
73 the binding supports the PLL dividers configuration in accordance with a
81 The CCU PLL dts-node uses the common clock bindings with no custom
83 'include/dt-bindings/clock/bt1-ccu.h'. Since CCU PLL is a part of the
89 const: baikal,bt1-ccu-pll
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| D | qcom,a53pll.yaml | 7 title: Qualcomm A53 PLL clock
13 The A53 PLL on few Qualcomm platforms is the main CPU PLL used used for
55 # Example 1 - A53 PLL found on MSM8916 devices
62 # Example 2 - A53 PLL found on IPQ6018 devices
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| D | fsl,qoriq-clock.yaml | 15 multiple phase locked loops (PLL) to create a variety of frequencies
92 4 platform pll n=pll/(n+1). For example, when n=1,
107 platform PLL.
124 '^pll[0-9]@[a-f0-9]+$':
128 '^platform\-pll@[a-f0-9]+$':
167 compatible = "fsl,qoriq-core-pll-1.0";
175 compatible = "fsl,qoriq-core-pll-1.0";
200 platform-pll@c00 {
203 compatible = "fsl,qoriq-platform-pll-1.0";
205 clock-output-names = "platform-pll", "platform-pll-div2";
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| D | dove-divider-clock.txt | 1 PLL divider based Dove clocks
3 Marvell Dove has a 2GHz PLL, which feeds into a set of dividers to provide
18 - reg : shall be the register address of the Core PLL and Clock Divider
20 Core PLL and Clock Divider Control 1 register. Thus, it will have
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| /Documentation/devicetree/bindings/sound/ |
| D | ti,pcm512x.yaml | 38 absent the device will be configured to clock from BCLK. If pll-in and
39 pll-out are specified in addition to a clock, the device is configured to
45 pll-in:
46 description: GPIO pin used to connect the pll using <1> through <6>. The
47 device will be configured for clock input on the given pll-in pin.
52 pll-out:
53 description: GPIO pin used to connect the pll using <1> through <6>. The
54 device will be configured for PLL output on the given pll-out pin. An
55 external connection from the pll-out pin to the SCLK pin is assumed.
77 pll-in:
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| /Documentation/devicetree/bindings/usb/ |
| D | nvidia,tegra210-xusb.yaml | 47 - description: USB PLL
49 - description: I/O PLL
120 avdd-pll-utmip-supply:
121 description: UTMI PLL power supply. Must supply 1.8 V.
123 avdd-pll-uerefe-supply:
124 description: PLLE reference PLL power supply. Must supply 1.05 V.
126 dvdd-usb-ss-pll-supply:
127 description: PCIe/USB3 PLL power supply. Must supply 1.05 V.
129 hvdd-usb-ss-pll-e-supply:
183 avdd-pll-utmip-supply = <&vdd_1v8>;
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| D | nvidia,tegra124-xusb.yaml | 55 - description: USB PLL
57 - description: I/O PLL
117 avdd-pll-utmip-supply:
118 description: UTMI PLL power supply. Must supply 1.8 V.
120 avdd-pll-erefe-supply:
121 description: PLLE reference PLL power supply. Must supply 1.05 V.
123 avdd-usb-ss-pll-supply:
124 description: PCIe/USB3 PLL power supply. Must supply 1.05 V.
129 hvdd-usb-ss-pll-e-supply:
195 avdd-pll-utmip-supply = <&vddio_1v8>;
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| /Documentation/devicetree/bindings/display/ |
| D | allwinner,sun4i-a10-hdmi.yaml | 38 - description: The first video PLL
39 - description: The second video PLL
45 - description: The first video PLL
46 - description: The second video PLL
53 - const: pll-0
54 - const: pll-1
60 - const: pll-0
61 - const: pll-1
138 clock-names = "ahb", "mod", "pll-0", "pll-1";
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| /Documentation/devicetree/bindings/display/ti/ |
| D | ti,dra7-dss.txt | 20 Some DRA7xx SoCs have one dedicated video PLL, some have two. These properties
25 - clocks: handle to video1 pll clock and video2 pll clock
60 - reg: addresses and lengths of the register spaces for 'wp', 'pll', 'phy',
62 - reg-names: "wp", "pll", "phy", "core"
66 - clocks: handles to fclk and pll clock
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