Searched full:pll4 (Results 1 – 12 of 12) sorted by relevance
| /Documentation/devicetree/bindings/clock/ |
| D | allwinner,sun9i-a80-pll4-clk.yaml | 4 $id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-pll4-clk.yaml#
20 const: allwinner,sun9i-a80-pll4-clk
44 compatible = "allwinner,sun9i-a80-pll4-clk";
47 clock-output-names = "pll4";
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| D | qcom,gcc-ipq8064.yaml | 34 - description: PLL4 from LCC
41 - const: pll4
66 clocks = <&pxo_board>, <&cxo_board>, <&lcc PLL4>;
67 clock-names = "pxo", "cxo", "pll4";
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| D | allwinner,sun9i-a80-apb0-clk.yaml | 50 clocks = <&osc24M>, <&pll4>;
59 clocks = <&osc24M>, <&pll4>;
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| D | allwinner,sun4i-a10-ve-clk.yaml | 51 clocks = <&pll4>;
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| D | allwinner,sun9i-a80-gt-clk.yaml | 48 clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>;
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| D | qcom,gcc-mdm9615.yaml | 31 - description: PLL4 from LLC
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| D | allwinner,sun9i-a80-ahb-clk.yaml | 48 clocks = <>_clk>, <&pll4>, <&pll12>, <&pll12>;
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| D | allwinner,sun9i-a80-cpus-clk.yaml | 48 clocks = <&osc32k>, <&osc24M>, <&pll4>, <&pll3>;
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| D | allwinner,sun4i-a10-mmc-clk.yaml | 82 clocks = <&osc24M>, <&pll4>;
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| D | qcom,gcc-apq8064.yaml | 48 - const: pll4
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| /Documentation/devicetree/bindings/sound/ |
| D | ti,j721e-cpb-audio.yaml | 19 clock for AUDIO_REFCLK2 needs to be changed between PLL4 (for 48KHz) and
25 PLL4 ---> PLL4_HSDIV0 ---> MCASP10_AUXCLK ---> McASP10.auxclk
34 PLL4 ---> PLL4_HSDIV0 ---> MCASP0_AUXCLK ---> McASP0.auxclk
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| D | ti,j721e-cpb-ivi-audio.yaml | 24 for AUDIO_REFCLK0 needs to be changed between PLL4 (for 48KHz) and PLL15 (for
28 Note: the same PLL4 and PLL15 is used by the audio support on the CPB!
31 PLL4 ---> PLL4_HSDIV0 ---> MCASP10_AUXCLK ---> McASP10.auxclk
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