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/Documentation/devicetree/bindings/clock/
Datmel,at91rm9200-pmc.yaml4 $id: http://devicetree.org/schemas/clock/atmel,at91rm9200-pmc.yaml#
7 title: Atmel Power Management Controller (PMC)
14 system and user peripheral clocks. The PMC enables/disables the clock inputs
21 - const: atmel,at91sam9g20-pmc
22 - const: atmel,at91sam9260-pmc
26 - atmel,at91sam9g15-pmc
27 - atmel,at91sam9g25-pmc
28 - atmel,at91sam9g35-pmc
29 - atmel,at91sam9x25-pmc
30 - atmel,at91sam9x35-pmc
[all …]
Dvt8500.txt16 - reg : shall be the control register offset from PMC base for the pll clock.
36 - enable-reg : shall be the register offset from PMC base for the enable
44 - divisor-reg : shall be the register offset from PMC base for the divisor
/Documentation/devicetree/bindings/powerpc/fsl/
Dpmc.txt4 - compatible: "fsl,<chip>-pmc".
6 "fsl,mpc8349-pmc" should be listed for any chip whose PMC is
7 compatible. "fsl,mpc8313-pmc" should also be listed for any chip
8 whose PMC is compatible, and implies deep-sleep capability.
10 "fsl,mpc8548-pmc" should be listed for any chip whose PMC is
11 compatible. "fsl,mpc8536-pmc" should also be listed for any chip
12 whose PMC is compatible, and implies deep-sleep capability.
14 "fsl,mpc8641d-pmc" should be listed for any chip whose PMC is
15 compatible; all statements below that apply to "fsl,mpc8548-pmc" also
16 apply to "fsl,mpc8641d-pmc".
[all …]
/Documentation/devicetree/bindings/soc/loongson/
Dloongson,ls2k-pmc.yaml4 $id: http://devicetree.org/schemas/soc/loongson/loongson,ls2k-pmc.yaml#
16 - const: loongson,ls2k0500-pmc
20 - loongson,ls2k1000-pmc
21 - loongson,ls2k2000-pmc
22 - const: loongson,ls2k0500-pmc
64 compatible = "loongson,ls2k1000-pmc", "loongson,ls2k0500-pmc", "syscon";
78 regmap = <&pmc>;
/Documentation/devicetree/bindings/arm/tegra/
Dnvidia,tegra186-pmc.yaml4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra186-pmc.yaml#
7 title: NVIDIA Tegra Power Management Controller (PMC)
16 - nvidia,tegra186-pmc
17 - nvidia,tegra194-pmc
18 - nvidia,tegra234-pmc
27 - const: pmc
49 const: nvidia,tegra186-pmc
63 const: nvidia,tegra194-pmc
75 const: nvidia,tegra234-pmc
90 attribute of the hardware. The PMC can be used to set pad power
[all …]
/Documentation/firmware-guide/acpi/
Dintel-pmc-mux.rst10 North Mux-Agent is a function of the Intel PMC firmware that is supported on
11 most Intel based platforms that have the PMC microcontroller. It's used for
16 The North Mux-Agent (aka. Intel PMC Mux Control, or just mux-agent) driver
17 communicates with the PMC microcontroller by using the PMC IPC method
31 is a separate child node under the PMC mux-agent device node. Those nodes do not
35 Scope (_SB.PCI0.PMC.MUX)
54 Scope (_SB.PCI0.PMC.MUX)
73 In order to configure the muxes behind a USB Type-C connector, the PMC firmware
80 the PMC::
117 Scope (_SB.PCI0.PMC)
Dindex.rst30 intel-pmc-mux
/Documentation/devicetree/bindings/soc/tegra/
Dnvidia,tegra20-pmc.yaml4 $id: http://devicetree.org/schemas/soc/tegra/nvidia,tegra20-pmc.yaml#
7 title: Tegra Power Management Controller (PMC)
16 - nvidia,tegra20-pmc
17 - nvidia,tegra30-pmc
18 - nvidia,tegra114-pmc
19 - nvidia,tegra124-pmc
20 - nvidia,tegra210-pmc
38 Tegra PMC has clk_out_1, clk_out_2, and clk_out_3. PMC also has blink
41 Consumer of PMC clock should specify the desired clock by having the
42 clock ID in its "clocks" phandle cell with PMC clock provider. See
[all …]
/Documentation/devicetree/bindings/arm/vt8500/
Dvia,vt8500-pmc.txt5 - compatible : "via,vt8500-pmc"
10 pmc@d8130000 {
11 compatible = "via,vt8500-pmc";
/Documentation/ABI/obsolete/
Dsysfs-driver-intel_pmc_bxt1 These files allow sending arbitrary IPC commands to the PMC/SCU which
10 IPC command to the PMC/SCU.
20 Northpeak through the PMC/SCU.
/Documentation/driver-api/xilinx/
Deemi.rst10 used by any driver to communicate with PMC(Platform Management Controller).
16 device to communicate with a power management controller (PMC) on a
19 Any driver who wants to communicate with PMC using EEMI APIs use the
/Documentation/devicetree/bindings/display/
Datmel,lcdc.yaml67 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_PERIPHERAL 23>;
/Documentation/devicetree/bindings/sound/
Dmicrochip,sama7g5-spdifrx.yaml74 clocks = <&pmc PMC_TYPE_PERIPHERAL 84>, <&pmc PMC_TYPE_GCK 84>;
Dmicrochip,sama7g5-spdiftx.yaml74 clocks = <&pmc PMC_TYPE_PERIPHERAL 85>, <&pmc PMC_TYPE_GCK 85>;
Dmicrochip,sama7g5-pdmc.yaml99 clocks = <&pmc PMC_TYPE_PERIPHERAL 68>, <&pmc PMC_TYPE_GCK 68>;
/Documentation/devicetree/bindings/thermal/
Dnvidia,tegra30-tsensor.yaml25 Generates a signal to the PMC when the temperature reaches dangerously high
26 levels to reset the chip and sets a flag in the PMC.
/Documentation/devicetree/bindings/gpio/
Dgpio-zynq.yaml18 - xlnx,pmc-gpio-1.0
85 - xlnx,pmc-gpio-1.0
/Documentation/ABI/testing/
Dsysfs-platform-intel-pmc13 Display global reset setting bits for PMC.
/Documentation/devicetree/bindings/media/
Dmicrochip,sama5d4-vdec.yaml46 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
/Documentation/devicetree/bindings/display/bridge/
Dmicrochip,sam9x75-lvds.yaml53 clocks = <&pmc PMC_TYPE_PERIPHERAL 56>;
/Documentation/devicetree/bindings/reset/
Datmel,at91sam9260-reset.yaml67 clocks = <&pmc PMC_TYPE_CORE PMC_SLOW>;
/Documentation/devicetree/bindings/crypto/
Datmel,at91sam9g46-sha.yaml60 clocks = <&pmc PMC_TYPE_PERIPHERAL 83>;
Datmel,at91sam9g46-aes.yaml65 clocks = <&pmc PMC_TYPE_PERIPHERAL 27>;
/Documentation/devicetree/bindings/phy/
Dnvidia,tegra20-usb-phy.yaml205 nvidia,pmc:
354 nvidia,pmc = <&tegra_pmc 2>;
372 nvidia,pmc = <&tegra_pmc 1>;
/Documentation/devicetree/bindings/pci/
Dsnps,dw-pcie-common.yaml98 Auxiliary clock for the controller PMC domain. The controller
162 Controller primary reset (resets everything except PMC module)
166 - description: PMC hot reset signal

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