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/Documentation/devicetree/bindings/interrupt-controller/
Dti,omap4-wugen-mpu20 - Only SPIs can use the WUGEN as an interrupt parent. SGIs and PPIs
Dnvidia,tegra20-ictlr.txt27 - Only SPIs can use the ictlr as an interrupt parent. SGIs and PPIs
Darm,gic.yaml17 Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.
19 have PPIs or SGIs.
Darm,gic-v3.yaml63 interrupt types other than PPI or PPIs that are not partitioned,
/Documentation/devicetree/bindings/timer/
Darm,arch_timer.yaml18 per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
/Documentation/virt/kvm/devices/
Darm-vgic-v3.rst284 PPIs are reported per VCPU as specified in the mpidr field, and SPIs are
/Documentation/virt/kvm/
Dapi.rst886 use PPIs designated for specific cpus. The irq field is interpreted