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/Documentation/ABI/testing/
Dsysfs-ptp1 What: /sys/class/ptp/
7 features of PTP hardware clocks.
9 What: /sys/class/ptp/ptp<N>/
13 This directory contains the attributes of the Nth PTP
14 hardware clock registered into the PTP class driver
17 What: /sys/class/ptp/ptp<N>/clock_name
21 This file contains the name of the PTP hardware clock
28 What: /sys/class/ptp/ptp<N>/max_adjustment
32 This file contains the PTP hardware clock's maximum
36 What: /sys/class/ptp/ptp<N>/max_vclocks
[all …]
/Documentation/devicetree/bindings/ptp/
Dbrcm,ptp-dte.txt1 * Broadcom Digital Timing Engine(DTE) based PTP clock
9 "brcm,ptp-dte"
11 "brcm,iproc-ptp-dte" - for iproc based SoC's
16 ptp: ptp-dte@180af650 {
17 compatible = "brcm,iproc-ptp-dte", "brcm,ptp-dte";
Dfsl,ptp.yaml4 $id: http://devicetree.org/schemas/ptp/fsl,ptp.yaml#
7 title: Freescale QorIQ 1588 timer based PTP clock
16 - fsl,etsec-ptp
17 - fsl,fman-ptp-timer
18 - fsl,dpaa2-ptp
21 - const: fsl,enetc-ptp
86 These properties set the operational parameters for the PTP
134 const: fsl,enetc-ptp
145 compatible = "fsl,etsec-ptp";
Dptp-idt82p33.yaml4 $id: http://devicetree.org/schemas/ptp/ptp-idt82p33.yaml#
7 title: IDT 82P33 PTP Clock
10 IDT 82P33XXX Synchronization Management Unit (SMU) based PTP clock
Dptp-ines.txt1 ZHAW InES PTP time stamping IP core
11 - compatible: "ines,ptp-ctrl"
22 compatible = "ines,ptp-ctrl";
Dptp-idtcm.yaml4 $id: http://devicetree.org/schemas/ptp/ptp-idtcm.yaml#
7 title: IDT ClockMatrix (TM) PTP Clock
/Documentation/devicetree/bindings/net/
Dintel,ixp46x-ptp-timer.yaml5 $id: http://devicetree.org/schemas/net/intel,ixp46x-ptp-timer.yaml#
8 title: Intel IXP46x PTP Timer (TSYNC)
14 The Intel IXP46x PTP timer is known in the manual as IEEE1588 Hardware
15 Assist and Time Synchronization Hardware Assist TSYNC provides a PTP
20 const: intel,ixp46x-ptp-timer
48 ptp-timer@c8010000 {
49 compatible = "intel,ixp46x-ptp-timer";
Dmscc,vsc7514-switch.yaml18 packets using CPU. Additionally, PTP is supported as well as FDMA for faster
61 - description: PTP target
86 - const: ptp
108 - description: PTP ready
153 reg-names = "sys", "rew", "qs", "ptp", "port0", "port1",
200 reg-names = "sys", "rew", "qs", "ptp", "port0", "port1",
Dmicrochip,lan966x-switch.yaml41 - description: ptp interrupt
42 - description: ptp external interrupt
50 - const: ptp
51 - const: ptp-ext
Dfsl,fman.yaml85 description: see ptp/fsl,ptp.yaml
136 $ref: /schemas/ptp/fsl,ptp.yaml
194 ptp-timer = <&ptp_timer>;
200 compatible = "fsl,fman-ptp-timer";
Dfsl-tsec-phy.txt87 * Gianfar PTP clock nodes
89 Refer to Documentation/devicetree/bindings/ptp/fsl,ptp.yaml
Dfsl,fman-dtsec.yaml84 ptp-timer:
156 ptp-timer = <&ptp_timer>;
165 ptp-timer = <&ptp_timer0>;
Dsnps,dwmac.yaml131 PTP reference clock. This clock is used for programming the
234 snps,route-ptp:
236 description: PTP Packets
268 snps,route-ptp: false
274 - snps,route-ptp
287 snps,route-ptp: false
296 snps,route-ptp: false
305 snps,route-ptp: false
/Documentation/driver-api/
Dptp.rst4 PTP hardware clock infrastructure for Linux
7 This patch set introduces support for IEEE 1588 PTP clocks in
9 presents a standardized method for developing PTP user space
11 ancillary features of PTP hardware clocks.
15 complete set of PTP hardware clock functionality.
29 PTP hardware clock kernel API
32 A PTP clock driver registers itself with the class driver. The
39 The class driver supports multiple PTP clock drivers. In normal use
40 cases, only one PTP clock is needed. However, for testing and
44 PTP hardware clock user space API
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/Documentation/devicetree/bindings/pinctrl/
Dmarvell,kirkwood-pinctrl.txt28 mpp4 4 gpio, nand(io6), uart0(rxd), ptp(clk)
29 mpp5 5 gpo, nand(io7), uart0(txd), ptp(trig)
30 mpp6 6 sysrst(out), spi(mosi), ptp(trig)
31 mpp7 7 gpo, pex(rsto), spi(cs), ptp(trig)
32 mpp8 8 gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
34 mpp9 9 gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
36 mpp10 10 gpo, spi(sck), uart0(txd), ptp(trig)
37 mpp11 11 gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
38 ptp-2(trig)
66 mpp4 4 gpio, nand(io6), uart0(rxd), ptp(clk)
[all …]
Dmarvell,armada-38x-pinctrl.txt32 mpp14 14 gpio, ge0(rxd2), ptp(clk), dram(vttctrl), spi0(cs3), dev(we1), pcie3(clkreq)
35 mpp17 17 gpio, ge0(rxclk), ptp(clk), ua1(rxd), spi0(sck), sata1(prsnt), sata0(prsnt)
36 mpp18 18 gpio, ge0(rxerr), ptp(trig), ua1(txd), spi0(cs0)
37 mpp19 19 gpio, ge0(col), ptp(evreq), ge0(txerr), sata1(prsnt), ua0(cts)
38 mpp20 20 gpio, ge0(txclk), ptp(clk), sata0(prsnt), ua0(rts)
54 mpp36 36 gpio, ptp(trig), dev(a0)
55 mpp37 37 gpio, ptp(clk), ge1(rxclk), sd0(d3), dev(ad8)
56 mpp38 38 gpio, ptp(evreq), ge1(rxd1), ref(clk_out0), sd0(d0), dev(ad4)
69 mpp51 51 gpio, tdm(dtx), audio(sdo), dram(deccerr), ptp(trig)
70 mpp52 52 gpio, pcie0(rstout), tdm(int), audio(sdi), sd0(d6), ptp(clk)
[all …]
Dmarvell,armada-375-pinctrl.txt18 mpp2 2 gpio, dev(ad4), ptp(evreq), led(c0), audio(sdi)
19 mpp3 3 gpio, dev(ad5), ptp(trig), led(p3), audio(mclk)
23 mpp7 7 gpio, dev(ad1), ptp(clk), led(p2), audio(extclk)
48 mpp32 32 gpio, ge1(txd2), spi1(sck), ptp(trig)
79 mpp63 63 gpio, ptp(trig), led(p2), dev(burst/last)
82 mpp66 66 gpio, ptp(evreq), spi1(cs3)
Dmarvell,armada-xp-pinctrl.txt39 mpp18 18 gpio, ge0(rxerr), ge1(rxd0), lcd(d18), ptp(trig)
40 mpp19 19 gpio, ge0(crs), ge1(rxd1), lcd(d19), ptp(evreq)
41 mpp20 20 gpio, ge0(rxd4), ge1(rxd2), lcd(d20), ptp(clk)
48 mpp27 27 gpio, lcd(e), tdm(dtx), ptp(trig)
49 mpp28 28 gpio, lcd(pwm), tdm(drx), ptp(evreq)
50 mpp29 29 gpio, lcd(ref-clk), tdm(int0), ptp(clk)
Dmarvell,armada-37xx-pinctrl.txt138 group ptp
140 - functions ptp, gpio
144 - functions ptp, mii
148 - functions ptp, mii
/Documentation/devicetree/bindings/arm/marvell/
Dcp110-system-controller.txt91 mpp0 0 gpio, dev(ale1), au(i2smclk), ge0(rxd3), tdm(pclk), ptp(pulse), mss_i2c(sda), uart0(rxd), sa…
92 mpp1 1 gpio, dev(ale0), au(i2sdo_spdifo), ge0(rxd2), tdm(drx), ptp(clk), mss_i2c(sck), uart0(txd), …
93 mpp2 2 gpio, dev(ad15), au(i2sextclk), ge0(rxd1), tdm(dtx), mss_uart(rxd), ptp(pclk_out), i2c1(sck)…
97 …1), ge0(txd3), spi0(csn2), au(i2sextclk), sata1(present_act), pcie2(clkreq), uart0(rxd), ptp(pulse)
98 …, dev(ad10), ge0(txd2), spi0(csn1), spi1(csn1), sata0(present_act), led(data), uart0(txd), ptp(clk)
99 mpp8 8 gpio, dev(ad9), ge0(txd1), spi0(csn0), spi1(csn0), uart0(cts), led(stb), uart2(rxd), ptp(pcl…
106 mpp15 15 gpio, dev(ad7), spi1(mosi), spi0(mosi), mss_spi(mosi), ptp(pulse_cp2cp)
109 mpp18 18 gpio, dev(ad4), ge0(txd2), ptp(clk_cp2cp)
119 mpp28 28 gpio, dev(csn1), spi1(csn0), mss_gpio5, ge0(rxd2), spi0(csn5), pcie2(clkreq), ptp(pulse), …
120 mpp29 29 gpio, dev(csn2), spi1(mosi), mss_gpio6, ge0(rxd1), spi0(csn6), pcie1(clkreq), ptp(clk), ms…
[all …]
/Documentation/security/tpm/
Dtpm_tis.rst7 TCG PTP Specification defines two interface types: FIFO and CRB. The former is
45 TCG PC Client Platform TPM Profile (PTP) Specification
46 https://trustedcomputinggroup.org/resource/pc-client-platform-tpm-profile-ptp-specification/
/Documentation/devicetree/bindings/net/dsa/
Dhirschmann,hellcreek.yaml30 The physical base address and size of TSN and PTP memory base
37 - const: ptp
85 reg-names = "tsn", "ptp";
/Documentation/devicetree/bindings/tpm/
Dtcg,tpm-tis-i2c.yaml21 TCG PC Client Platform TPM Profile Specification for TPM 2.0 (PTP)
22 https://trustedcomputinggroup.org/resource/pc-client-platform-tpm-profile-ptp-specification/
30 - description: Generic TPM 2.0 chips conforming to TCG PTP interface
Dgoogle,cr50.yaml19 TCG PC Client Platform TPM Profile Specification for TPM 2.0 (PTP), sec 6:
20 https://trustedcomputinggroup.org/resource/pc-client-platform-tpm-profile-ptp-specification/
/Documentation/networking/
Dtimestamping.rst428 a HW PTP clock source, to allow time conversion in userspace and
429 optionally synchronize system time with a userspace PTP stack such
430 as linuxptp. For the PTP clock API, see Documentation/driver-api/ptp.rst.
587 /* PTP v1, UDP, any kind of event packet */
643 3.2 Special considerations for stacked PTP Hardware Clocks
646 There are situations when there may be more than one PHC (PTP Hardware Clock)
663 When a DSA switch is attached to a host port, PTP synchronization has to
665 jitter between the host port and its PTP partner. For this reason, some DSA
674 By design, PTP timestamping with a DSA switch does not need any special
676 host port also supports PTP timestamping, DSA will take care of intercepting
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