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/Documentation/devicetree/bindings/pwm/
Dpwm.txt1 Specifying PWM information for devices
4 1) PWM user nodes
7 PWM users should specify a list of PWM devices that they want to use
8 with a property containing a 'pwm-list':
10 pwm-list ::= <single-pwm> [pwm-list]
11 single-pwm ::= <pwm-phandle> <pwm-specifier>
12 pwm-phandle : phandle to PWM controller node
13 pwm-specifier : array of #pwm-cells specifying the given PWM
16 PWM properties should be named "pwms". The exact meaning of each pwms
18 An optional property "pwm-names" may contain a list of strings to label
[all …]
Dpwm-amlogic.yaml4 $id: http://devicetree.org/schemas/pwm/pwm-amlogic.yaml#
7 title: Amlogic PWM
16 - amlogic,meson8b-pwm
17 - amlogic,meson-gxbb-pwm
18 - amlogic,meson-gxbb-ao-pwm
19 - amlogic,meson-axg-ee-pwm
20 - amlogic,meson-axg-ao-pwm
21 - amlogic,meson-g12a-ee-pwm
22 - amlogic,meson-g12a-ao-pwm-ab
23 - amlogic,meson-g12a-ao-pwm-cd
[all …]
Dpwm-samsung.yaml4 $id: http://devicetree.org/schemas/pwm/pwm-samsung.yaml#
7 title: Samsung SoC PWM timers
14 Samsung SoCs contain PWM timer blocks which can be used for system clock source
15 and clock event timers, as well as to drive SoC outputs with PWM signal. Each
16 PWM timer block provides 5 PWM channels (not all of them can drive physical
25 - samsung,s3c2410-pwm # 16-bit, S3C24xx
26 - samsung,s3c6400-pwm # 32-bit, S3C64xx
27 - samsung,s5p6440-pwm # 32-bit, S5P64x0
28 - samsung,s5pc100-pwm # 32-bit, S5PC100, S5PV210, Exynos4210 rev0 SoCs
29 - samsung,exynos4210-pwm # 32-bit, Exynos
[all …]
Dimx-pwm.yaml4 $id: http://devicetree.org/schemas/pwm/imx-pwm.yaml#
7 title: Freescale i.MX PWM controller
13 - $ref: pwm.yaml#
16 "#pwm-cells":
19 PWM_POLARITY_INVERTED. fsl,imx1-pwm does not support this flags.
25 - fsl,imx1-pwm
26 - fsl,imx27-pwm
29 - fsl,imx25-pwm
30 - fsl,imx31-pwm
31 - fsl,imx50-pwm
[all …]
Drenesas,pwm-rcar.yaml4 $id: http://devicetree.org/schemas/pwm/renesas,pwm-rcar.yaml#
7 title: Renesas R-Car PWM Timer Controller
16 - renesas,pwm-r8a7742 # RZ/G1H
17 - renesas,pwm-r8a7743 # RZ/G1M
18 - renesas,pwm-r8a7744 # RZ/G1N
19 - renesas,pwm-r8a7745 # RZ/G1E
20 - renesas,pwm-r8a77470 # RZ/G1C
21 - renesas,pwm-r8a774a1 # RZ/G2M
22 - renesas,pwm-r8a774b1 # RZ/G2N
23 - renesas,pwm-r8a774c0 # RZ/G2E
[all …]
Dpwm-rockchip.yaml4 $id: http://devicetree.org/schemas/pwm/pwm-rockchip.yaml#
7 title: Rockchip PWM controller
15 - const: rockchip,rk2928-pwm
16 - const: rockchip,rk3288-pwm
17 - const: rockchip,rk3328-pwm
18 - const: rockchip,vop-pwm
20 - const: rockchip,rk3036-pwm
21 - const: rockchip,rk2928-pwm
24 - rockchip,rk3128-pwm
25 - rockchip,rk3368-pwm
[all …]
Dallwinner,sun4i-a10-pwm.yaml4 $id: http://devicetree.org/schemas/pwm/allwinner,sun4i-a10-pwm.yaml#
7 title: Allwinner A10 PWM
14 "#pwm-cells":
19 - const: allwinner,sun4i-a10-pwm
20 - const: allwinner,sun5i-a10s-pwm
21 - const: allwinner,sun5i-a13-pwm
22 - const: allwinner,sun7i-a20-pwm
23 - const: allwinner,sun8i-h3-pwm
25 - const: allwinner,sun8i-a83t-pwm
26 - const: allwinner,sun8i-h3-pwm
[all …]
Dnvidia,tegra20-pwm.yaml4 $id: http://devicetree.org/schemas/pwm/nvidia,tegra20-pwm.yaml#
17 - nvidia,tegra20-pwm
18 - nvidia,tegra186-pwm
22 - nvidia,tegra30-pwm
23 - nvidia,tegra114-pwm
24 - nvidia,tegra124-pwm
25 - nvidia,tegra132-pwm
26 - nvidia,tegra210-pwm
28 - nvidia,tegra20-pwm
31 - const: nvidia,tegra194-pwm
[all …]
Dpwm-sifive.yaml5 $id: http://devicetree.org/schemas/pwm/pwm-sifive.yaml#
8 title: SiFive PWM controller
14 Unlike most other PWM controllers, the SiFive PWM controller currently
15 only supports one period for all channels in the PWM. All PWMs need to
18 achievable period. PWM RTL that corresponds to the IP block version
21 https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/pwm
24 - $ref: pwm.yaml#
30 - sifive,fu540-c000-pwm
31 - sifive,fu740-c000-pwm
34 Should be "sifive,<chip>-pwm" and "sifive,pwm<version>". Supported
[all …]
Datmel,at91sam-pwm.yaml5 $id: http://devicetree.org/schemas/pwm/atmel,at91sam-pwm.yaml#
8 title: Atmel/Microchip PWM controller
14 - $ref: pwm.yaml#
21 - atmel,at91sam9rl-pwm
22 - atmel,sama5d3-pwm
23 - atmel,sama5d2-pwm
24 - microchip,sam9x60-pwm
27 - microchip,sama7d65-pwm
28 - microchip,sama7g5-pwm
29 - const: atmel,sama5d2-pwm
[all …]
Dmediatek,mt2712-pwm.yaml4 $id: http://devicetree.org/schemas/pwm/mediatek,mt2712-pwm.yaml#
7 title: MediaTek PWM Controller
13 - $ref: pwm.yaml#
19 - mediatek,mt2712-pwm
20 - mediatek,mt6795-pwm
21 - mediatek,mt7622-pwm
22 - mediatek,mt7623-pwm
23 - mediatek,mt7628-pwm
24 - mediatek,mt7629-pwm
25 - mediatek,mt7981-pwm
[all …]
Dmediatek,pwm-disp.yaml4 $id: http://devicetree.org/schemas/pwm/mediatek,pwm-disp.yaml#
13 - $ref: pwm.yaml#
19 - mediatek,mt2701-disp-pwm
20 - mediatek,mt6595-disp-pwm
21 - mediatek,mt8173-disp-pwm
22 - mediatek,mt8183-disp-pwm
25 - mediatek,mt6795-disp-pwm
26 - mediatek,mt8167-disp-pwm
27 - const: mediatek,mt8173-disp-pwm
30 - mediatek,mt8186-disp-pwm
[all …]
Dpwm.yaml4 $id: http://devicetree.org/schemas/pwm/pwm.yaml#
7 title: PWM controllers (providers)
16 pattern: "^pwm(@.*|-([0-9]|[1-9][0-9]+))?$"
18 "#pwm-cells":
20 Number of cells in a PWM specifier. Typically the cells represent, in
21 order: the chip-relative PWM number, the PWM period in nanoseconds and
22 optionally a number of flags (defined in <dt-bindings/pwm/pwm.h>).
25 - "#pwm-cells"
31 pwm: pwm@1c20e00 {
32 compatible = "allwinner,sun7i-a20-pwm";
[all …]
Dpwm-hibvt.txt1 Hisilicon PWM controller
6 "hisilicon,hi3516cv300-pwm"
7 "hisilicon,hi3519v100-pwm"
8 "hisilicon,hi3559v100-shub-pwm"
9 "hisilicon,hi3559v100-pwm
11 - clocks: phandle and clock specifier of the PWM reference clock.
12 - resets: phandle and reset specifier for the PWM controller reset.
13 - #pwm-cells: Should be 3. See pwm.yaml in this directory for a description of
17 pwm: pwm@12130000 {
18 compatible = "hisilicon,hi3516cv300-pwm";
[all …]
Dmxs-pwm.yaml4 $id: http://devicetree.org/schemas/pwm/mxs-pwm.yaml#
7 title: Freescale MXS PWM controller
13 - $ref: pwm.yaml#
18 - const: fsl,imx23-pwm
21 - fsl,imx28-pwm
22 - const: fsl,imx23-pwm
30 "#pwm-cells":
33 fsl,pwm-number:
35 description: u32 value representing the number of PWM devices
41 - fsl,pwm-number
[all …]
Dimg-pwm.txt1 *Imagination Technologies PWM DAC driver
4 - compatible: Should be "img,pistachio-pwm"
5 - reg: Should contain physical base address and length of pwm registers.
9 - pwm: PWM operating clock.
10 - sys: PWM system interface clock.
11 - #pwm-cells: Should be 2. See pwm.yaml in this directory for the
14 syscon node which contains PWM control registers.
17 pwm: pwm@18101300 {
18 compatible = "img,pistachio-pwm";
21 clock-names = "pwm", "sys";
[all …]
Dpwm-lp3943.txt1 TI/National Semiconductor LP3943 PWM controller
4 - compatible: "ti,lp3943-pwm"
5 - #pwm-cells: Should be 2. See pwm.yaml in this directory for a
9 - ti,pwm0 or ti,pwm1: Output pin number(s) for PWM channel 0 or 1.
17 PWM 0 is for RGB LED brightness control
18 PWM 1 is for brightness control of LP8557 backlight device
26 * PWM 0 : output 8, 9 and 10
27 * PWM 1 : output 15
29 pwm3943: pwm {
30 compatible = "ti,lp3943-pwm";
[all …]
Dcirrus,ep9301-pwm.yaml4 $id: http://devicetree.org/schemas/pwm/cirrus,ep9301-pwm.yaml#
7 title: Cirrus Logic ep93xx PWM controller
14 - $ref: pwm.yaml#
19 - const: cirrus,ep9301-pwm
22 - cirrus,ep9302-pwm
23 - cirrus,ep9307-pwm
24 - cirrus,ep9312-pwm
25 - cirrus,ep9315-pwm
26 - const: cirrus,ep9301-pwm
33 - description: SoC PWM clock
[all …]
Dopencores,pwm.yaml4 $id: http://devicetree.org/schemas/pwm/opencores,pwm.yaml#
7 title: OpenCores PWM controller
13 The OpenCores PTC ip core contains a PWM controller. When operating in PWM
18 - $ref: pwm.yaml#
24 - starfive,jh7100-pwm
25 - starfive,jh7110-pwm
26 - starfive,jh8100-pwm
27 - const: opencores,pwm-v1
38 "#pwm-cells":
50 pwm@12490000 {
[all …]
Dgoogle,cros-ec-pwm.yaml4 $id: http://devicetree.org/schemas/pwm/google,cros-ec-pwm.yaml#
7 title: PWM controlled by ChromeOS EC
14 Google's ChromeOS EC PWM is a simple PWM attached to the Embedded Controller
16 An EC PWM node should be only found as a sub-node of the EC node (see
20 - $ref: pwm.yaml#
25 - description: PWM controlled using EC_PWM_TYPE_GENERIC channels.
27 - const: google,cros-ec-pwm
28 - description: PWM controlled using CROS_EC_PWM_DT_<...> types.
30 - const: google,cros-ec-pwm-type
32 "#pwm-cells":
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Dlpc1850-sct-pwm.txt4 - compatible: Should be "nxp,lpc1850-sct-pwm"
5 - reg: Should contain physical base address and length of pwm registers.
9 - pwm: PWM operating clock.
10 - #pwm-cells: Should be 3. See pwm.yaml in this directory for the description
14 pwm: pwm@40000000 {
15 compatible = "nxp,lpc1850-sct-pwm";
18 clock-names = "pwm";
19 #pwm-cells = <3>;
/Documentation/ABI/testing/
Dsysfs-class-pwm1 What: /sys/class/pwm/
6 The pwm/ class sub-directory belongs to the Generic PWM
7 Framework and provides a sysfs interface for using PWM
10 What: /sys/class/pwm/pwmchip<N>/
15 A /sys/class/pwm/pwmchipN directory is created for each
16 probed PWM controller/chip where N is the base of the
17 PWM chip.
19 What: /sys/class/pwm/pwmchip<N>/npwm
24 The number of PWM channels supported by the PWM chip.
26 What: /sys/class/pwm/pwmchip<N>/export
[all …]
/Documentation/driver-api/
Dpwm.rst2 Pulse Width Modulation (PWM) interface
5 This provides an overview about the Linux PWM interface
9 the Linux PWM API (although they could). However, PWMs are often
12 this kind of flexibility the generic PWM API exists.
17 Users of the legacy PWM API use unique IDs to refer to PWM devices.
19 Instead of referring to a PWM device via its unique ID, board setup code
20 should instead register a static mapping that can be used to match PWM
24 PWM_LOOKUP("tegra-pwm", 0, "pwm-backlight", NULL,
39 consumer name. pwm_put() is used to free the PWM device. Managed variants of
42 After being requested, a PWM has to be configured using::
[all …]
/Documentation/hwmon/
Dadt7470.rst25 There are four (4) PWM outputs that can be used to control fan speed.
27 A sophisticated control system for the PWM outputs is designed into the ADT7470
29 temperature sensors. Each PWM output is individually adjustable and
30 programmable. Once configured, the ADT7470 will adjust the PWM outputs in
32 feature can also be disabled for manual control of the PWM's.
40 automatic fan pwm control to set the fan speed. The driver will not read the
51 determining an optimal configuration for the automatic PWM control.
58 * PWM Control
60 * pwm#_auto_point1_pwm and pwm#_auto_point1_temp and
61 * pwm#_auto_point2_pwm and pwm#_auto_point2_temp -
[all …]
Dpwm-fan.rst1 Kernel driver pwm-fan
4 This driver enables the use of a PWM module to drive a fan. It uses the
5 generic PWM interface thus it is hardware independent. It can be used on
6 many SoCs, as long as the SoC supplies a PWM line driver that exposes
7 the generic PWM API.
15 a PWM output. It uses the generic PWM interface, thus it can be used with
27 0 -> disable pwm and regulator
28 1 -> enable pwm; if pwm==0, disable pwm, keep regulator enabled
29 2 -> enable pwm; if pwm==0, keep pwm and regulator enabled
30 3 -> enable pwm; if pwm==0, disable pwm and regulator

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