Searched full:parents (Results 1 – 25 of 117) sorted by relevance
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| /Documentation/devicetree/bindings/phy/ |
| D | ti,phy-j721e-wiz.yaml | 98 assigned-clock-parents:
105 - assigned-clock-parents
134 assigned-clock-parents:
141 - assigned-clock-parents
211 assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;
220 assigned-clock-parents = <&k3_clks 293 13>;
227 assigned-clock-parents = <&k3_clks 293 0>;
245 assigned-clock-parents = <&k3_clks 292 11>;
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| D | mixel,mipi-dsi-phy.yaml | 66 - assigned-clock-parents
77 assigned-clock-parents: false
94 assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>;
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| D | ti,phy-am654-serdes.yaml | 73 - assigned-clock-parents
94 assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>;
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| /Documentation/devicetree/bindings/sound/ |
| D | nvidia,tegra-audio-graph-card.yaml | 39 assigned-clock-parents:
64 - assigned-clock-parents
82 assigned-clock-parents = <0>, <0>, <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
102 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
172 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
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| D | nvidia,tegra210-dmic.yaml | 48 assigned-clock-parents:
80 - assigned-clock-parents
94 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
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| D | nvidia,tegra186-dspk.yaml | 48 assigned-clock-parents:
80 - assigned-clock-parents
95 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
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| D | nvidia,tegra210-ahub.yaml | 46 assigned-clock-parents:
123 - assigned-clock-parents
140 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
177 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
188 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
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| D | nvidia,tegra210-i2s.yaml | 62 assigned-clock-parents:
96 - assigned-clock-parents
110 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
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| D | brcm,cygnus-audio.txt | 14 - assigned-clock-parents: parent clocks of the assigned clocks
40 assigned-clock-parents = <&audiopll BCM_CYGNUS_AUDIOPLL>;
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| /Documentation/devicetree/bindings/ufs/ |
| D | ti,j721e-ufs.yaml | 31 assigned-clock-parents:
72 assigned-clock-parents = <&k3_clks 277 4>;
86 assigned-clock-parents = <&k3_clks 277 4>;
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| /Documentation/devicetree/bindings/media/ |
| D | mediatek,vcodec-encoder.yaml | 47 assigned-clock-parents: true
83 - assigned-clock-parents
165 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>;
185 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>;
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| D | mediatek,vcodec-subdev-decoder.yaml | 127 assigned-clock-parents:
140 - assigned-clock-parents
238 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
264 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
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| /Documentation/devicetree/bindings/pwm/ |
| D | imx-tpm-pwm.yaml | 35 assigned-clock-parents:
56 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
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| D | pwm-sprd.txt | 17 - assigned-clock-parents: The phandle of the parent clock of PWM clock.
35 assigned-clock-parents = <&ext_26m>,
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| /Documentation/filesystems/ |
| D | directory-locking.rst | 56 * if the parents don't have a common ancestor, fail the operation.
57 * lock the parents in "ancestors first" order (exclusive). If neither is an
111 parents have a common ancestor.
214 cross-directory rename; parents first, then possibly their children.
218 It can't be the parents - indeed, since D1 is an ancestor of Dn,
222 locking the parents.
225 a loop, since the parents are locked before the children, so the parent
241 suppose the parents are initially in different trees; we would lock the
267 chains of ancestors of (ex-)parents of source and target. In particular,
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| /Documentation/devicetree/bindings/spmi/ |
| D | mtk,spmi-mtk-pmif.yaml | 51 assigned-clock-parents:
79 assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
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| /Documentation/devicetree/bindings/arm/ |
| D | sp810.yaml | 54 assigned-clock-parents:
78 assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>,
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| /Documentation/devicetree/bindings/rtc/ |
| D | st,stm32-rtc.yaml | 51 assigned-clock-parents:
133 assigned-clock-parents: false
155 assigned-clock-parents = <&rcc 1 CLK_LSE>;
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| /Documentation/devicetree/bindings/media/i2c/ |
| D | sony,imx334.yaml | 28 assigned-clock-parents: true
78 assigned-clock-parents = <&imx334_clk_parent>;
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| D | sony,imx412.yaml | 30 assigned-clock-parents: true
90 assigned-clock-parents = <&imx412_clk_parent>;
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| D | ovti,ov9282.yaml | 31 assigned-clock-parents: true
91 assigned-clock-parents = <&ov9282_clk_parent>;
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| D | sony,imx335.yaml | 28 assigned-clock-parents: true
90 assigned-clock-parents = <&imx335_clk_parent>;
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| /Documentation/devicetree/bindings/clock/ti/ |
| D | mux.txt | 5 parents, one of which can be selected as output. This clock does not
8 By default the "clocks" property lists the parents in the same order
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| /Documentation/devicetree/bindings/display/imx/ |
| D | nxp,imx8mq-dcss.yaml | 65 assigned-clock-parents:
98 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>, <&clk IMX8MQ_SYS1_PLL_800M>,
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| /Documentation/devicetree/bindings/clock/ |
| D | qcom,krait-cc.txt | 20 Definition: reference to the clock parents of hfpll, secondary muxes.
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