| /Documentation/devicetree/bindings/mmc/ |
| D | samsung,exynos-dw-mshc.yaml | 61 - description: CIU clock phase shift value for tx mode
64 - description: CIU clock phase shift value for rx mode
68 The value of CUI clock phase shift value in transmit mode and CIU clock
69 phase shift value in receive mode for double data rate mode operation.
75 - description: CIU clock phase shift value for tx mode
78 - description: CIU clock phase shift value for rx mode
82 The value of CIU TX and RX clock phase shift value for HS400 mode
85 - valid value for tx phase shift and rx phase shift is 0 to 7.
86 - when CIU clock divider value is set to 3, all possible 8 phase shift
89 phase shift clocks should be 0.
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| D | synopsys-dw-mshc.yaml | 46 - description: register offset that controls the SDMMC clock phase
50 that contains the SDMMC clock-phase control register. The first value is
52 SDMMC clock phase register, and the 3rd value is the bit shift for the
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| /Documentation/devicetree/bindings/watchdog/ |
| D | realtek,otto-wdt.yaml | 15 minimum duration of each phase is one tick. Each phase can trigger an
16 interrupt, although the phase 2 interrupt will occur with the system reset.
17 - Phase 1: During this phase, the WDT can be pinged to reset the timeout.
18 - Phase 2: Starts after phase 1 has timed out, and only serves to give the
20 During this phase, pinging the WDT has no effect, and a reset is
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| /Documentation/ABI/testing/ |
| D | sysfs-driver-zynqmp-fpga | 57 Phase 0 = 000
58 Phase 1 = 001
59 Phase 2 = 011
60 Phase 3 = 010
61 Phase 4 = 110
62 Phase 5 = 111
63 Phase 6 = 101
64 Phase 7 = 100
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| D | sysfs-bus-iio-dac-ltc2688 | 9 - change dither parameters (eg: frequency, phase...);
49 Sets the dither signal phase. Units are in Radians.
55 Returns the available values for the dither phase.
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| /Documentation/devicetree/bindings/spi/ |
| D | samsung,spi-peripheral-props.yaml | 23 The sampling phase shift to be applied on the miso line (to account
25 - 0: No phase shift.
26 - 1: 90 degree phase shift sampling.
27 - 2: 180 degree phase shift sampling.
28 - 3: 270 degree phase shift sampling.
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| /Documentation/devicetree/bindings/iio/proximity/ |
| D | semtech,sx9324.yaml | 45 Value indicates how each CS pin is used during phase 0.
59 description: Same as ph0-pin for phase 1.
67 description: Same as ph0-pin for phase 2.
75 description: Same as ph0-pin for phase 3.
86 Capacitance measurement resolution. For phase 0 and 1.
94 Capacitance measurement resolution. For phase 2 and 3
102 Phase used for start-up proximity detection.
103 It is used when we enable a phase to remove static offset and measure
112 PROXRAW filter strength for phase 0 and 1. A value of 0 represents off,
121 Same as proxraw-strength01, for phase 2 and 3.
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| /Documentation/devicetree/bindings/timer/ |
| D | renesas,rz-mtu3.yaml | 31 - Up to 12-phase PWM output in combination with synchronous operation
36 - Phase counting mode can be specified independently
37 - 32-bit phase counting mode can be specified for interlocked operation
57 - 32-bit phase counting mode specifiable by combining MTU1 and MTU2 and
75 There are two phase counting modes. 16-bit phase counting mode in which
76 MTU1 and MTU2 operate independently, and cascade connection 32-bit phase
79 In phase counting mode, the phase difference between two external input
83 count0 - MTU1 16-bit phase counting
84 count1 - MTU2 16-bit phase counting
85 count2 - MTU1+ MTU2 32-bit phase counting
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| /Documentation/netlink/specs/ |
| D | dpll.yaml | 176 doc: pin connected, active input of phase locked loop
203 name: phase-offset-divider
206 phase offset divider allows userspace to calculate a value of
207 measured signal phase difference between a pin and dpll device
210 integer part of a measured phase offset value.
212 fractional part of a measured phase offset value.
327 name: phase-adjust-min
330 name: phase-adjust-max
333 name: phase-adjust
336 name: phase-offset
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| /Documentation/devicetree/bindings/leds/backlight/ |
| D | sky81452-backlight.txt | 14 - skyworks,phase-shift : Enable phase shift mode
27 skyworks,phase-shift;
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| /Documentation/devicetree/bindings/memory-controllers/ |
| D | intel,ixp4xx-expansion-peripheral-props.yaml | 19 description: Address timing, extend address phase with n cycles.
24 description: Setup chip select timing, extend setup phase with n cycles.
29 description: Strobe timing, extend strobe phase with n cycles.
34 description: Hold timing, extend hold phase with n cycles.
39 description: Recovery timing, extend recovery phase with n cycles.
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| D | st,stm32-fmc2-ebi-props.yaml | 90 phase in nanoseconds used for asynchronous read/write transactions.
94 phase in nanoseconds used for asynchronous multiplexed read/write
98 description: This property defines the duration of the data setup phase
106 description: This property defines the duration of the data hold phase
119 phase in nanoseconds used for asynchronous write transactions.
123 phase in nanoseconds used for asynchronous multiplexed write
128 phase in nanoseconds used for asynchronous write transactions.
135 description: This property defines the duration of the data hold phase
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| /Documentation/devicetree/bindings/ |
| D | trivial-devices.yaml | 132 # Infineon Multi-phase Digital VR Controller xdpe11280
134 # Infineon Multi-phase Digital VR Controller xdpe12254
136 # Infineon Multi-phase Digital VR Controller xdpe12284
138 # Infineon Multi-phase Digital VR Controller xdpe15284
140 # Infineon Multi-phase Digital VR Controller xdpe152c4
274 # Monolithic Power Systems Inc. multi-phase controller mp2856
276 # Monolithic Power Systems Inc. multi-phase controller mp2857
278 # Monolithic Power Systems Inc. multi-phase controller mp2888
280 # Monolithic Power Systems Inc. multi-phase controller mp2891
282 # Monolithic Power Systems Inc. multi-phase controller mp2971
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| /Documentation/devicetree/bindings/sound/ |
| D | maxim,max98504.yaml | 45 and "timed hold" phase, the value must be from 0...6 (dB) range.
51 Brownout attack hold phase time in ms, VBATBROWN_ATTK_HOLD, register 0x0018.
57 Brownout timed hold phase time in ms, VBATBROWN_TIME_HOLD, register 0x0019.
63 Brownout release phase step time in ms, VBATBROWN_RELEASE, register 0x001A.
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| /Documentation/devicetree/bindings/regulator/ |
| D | dlg,da9121.yaml | 13 Dialog Semiconductor DA9121 Single-channel 10A double-phase buck converter
14 Dialog Semiconductor DA9122 Double-channel 5A single-phase buck converter
15 Dialog Semiconductor DA9220 Double-channel 3A single-phase buck converter
16 Dialog Semiconductor DA9217 Single-channel 6A double-phase buck converter
17 Dialog Semiconductor DA9130 Single-channel 10A double-phase buck converter
18 Dialog Semiconductor DA9131 Double-channel 5A single-phase buck converter
19 Dialog Semiconductor DA9132 Double-channel 3A single-phase buck converter
20 Dialog Semiconductor DA9141 Single-channel 40A quad-phase buck converter
21 Dialog Semiconductor DA9142 Single-channel 20A double-phase buck converter
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| /Documentation/devicetree/bindings/clock/ |
| D | altr_socfpga.txt | 26 - clk-phase : For the sdmmc_clk, contains the value of the clock phase that controls
28 value is the cclk_in_drv(drvsel). The clk-phase is used to enable the correct
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| /Documentation/driver-api/pm/ |
| D | devices.rst | 234 always go together, and both are multi-phase operations.
271 sleep states and the hibernation state ("suspend-to-disk"). Each phase involves
272 executing callbacks for every device before the next phase begins. Not all
285 rules are used to determine which callback to execute in the given phase:
318 1. The ``prepare`` phase is meant to prevent races by preventing new
323 suspend-related phases, during the ``prepare`` phase the device
393 4. The ``suspend_noirq`` phase occurs after IRQ handlers have been disabled,
402 an error during the suspend phase by fielding a shared interrupt
432 generally means undoing the actions of the ``suspend_noirq`` phase. If
446 the preceding ``suspend_late`` phase.
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| /Documentation/bpf/libbpf/ |
| D | libbpf_overview.rst | 42 The following section provides a brief overview of each phase in the BPF life
45 * **Open phase**: In this phase, libbpf parses the BPF
51 * **Load phase**: In the load phase, libbpf creates BPF
55 executed. After the load phase, it’s possible to set up the initial BPF map
58 * **Attachment phase**: In this phase, libbpf
61 phase, BPF programs perform useful work such as processing
65 * **Tear down phase**: In the tear down phase,
104 BPF programs before the BPF load phase and fetch and update data from user
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| /Documentation/hwmon/ |
| D | pmbus-core.rst | 174 int (*read_word_data)(struct i2c_client *client, int page, int phase,
177 Read word from page <page>, phase <phase>, register <reg>. If the chip does not
178 support multiple phases, the phase parameter can be ignored. If the chip
179 supports multiple phases, a phase value of 0xff indicates all phases.
216 int pmbus_set_page(struct i2c_client *client, u8 page, u8 phase);
218 Set PMBus page register to <page> and <phase> for subsequent commands.
219 If the chip does not support multiple phases, the phase parameter is
220 ignored. Otherwise, a phase value of 0xff selects all phases.
224 int pmbus_read_word_data(struct i2c_client *client, u8 page, u8 phase,
227 Read word data from <page>, <phase>, <reg>. Similar to
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| D | mpq8785.rst | 19 40A output current per phase, with excellent load and line regulation over a
26 The MPQ8785 adopts MPS's proprietary multi-phase digital constant-on-time (MCOT)
29 with excellent current sharing and phase interleaving for high-current
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| D | mp2888.rst | 20 vendor dual-loop, digital, multi-phase controller MP2888.
25 - Programmable Multi-Phase up to 10 Phases.
42 - for phase current: input and label.
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| D | mp2975.rst | 20 vendor dual-loop, digital, multi-phase controller MP2975.
26 to 8-phase operation for rail 1 and up to 4-phase operation for rail
54 - for phase current: input and label.
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| /Documentation/driver-api/ |
| D | dpll.rst | 10 PLL - Phase Locked Loop is an electronic circuit which syntonizes clock
14 DPLL - Digital Phase Locked Loop is an integrated circuit which in
15 addition to plain PLL behavior incorporates a digital phase detector
176 Phase offset measurement and adjustment
179 Device may provide ability to measure a phase difference between signals
180 on a pin and its parent dpll device. If pin-dpll phase offset measurement
184 Device may also provide ability to adjust a signal phase on a pin.
185 If pin phase adjustment is supported, minimal and maximal values that pin
188 attributes. Configured phase adjust value is provided with
194 ``DPLL_A_PIN_PHASE_ADJUST_MIN`` attr minimum value of phase adjustment
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| /Documentation/devicetree/bindings/power/supply/ |
| D | rohm,bd99954.yaml | 36 # First a constant current (5) phase (CC)
37 # Then constant voltage (CV) phase (after the battery voltage has reached
71 # Current used at trickle-charge phase (8 in above chart)
76 # Current used at pre-charge phase (6 in above chart)
81 # Current used at fast charge constant current phase (5 in above chart)
86 # The constant voltage used in fast charging phase (4 in above chart)
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| /Documentation/driver-api/media/drivers/ |
| D | radiotrack.rst | 105 0 0 "zero" bit phase 1
106 0 1 "zero" bit phase 2
107 1 0 "one" bit phase 1
108 1 1 "one" bit phase 2
161 disable, "zero" bit phase 1, tuner adjust)
163 disable, "zero" bit phase 2, tuner adjust)
166 disable, "one" bit phase 1, tuner adjust)
168 disable, "one" bit phase 2, tuner adjust)
|