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| /Documentation/devicetree/bindings/pinctrl/ |
| D | pinmux-node.yaml | 7 title: Generic Pin Multiplexing Node
13 The contents of the pin configuration child nodes are defined by the binding
14 for the individual pin controller device. The pin configuration nodes need not
15 be direct children of the pin controller device; they may be grandchildren,
18 the binding for the individual pin controller device.
20 While not required to be used, there are 3 generic forms of pin muxing nodes
21 which pin controller devices can use.
23 pin multiplexing nodes:
45 pin controller hardware. For hardware where there is a large number of identical
46 pin controller instances, naming each pin and function can easily become
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| D | pinctrl-bindings.txt | 3 Hardware modules that control pin multiplexing or configuration parameters
4 such as pull-up/down, tri-state, drive-strength etc are designated as pin
5 controllers. Each pin controller must be represented as a node in device tree,
8 Hardware modules whose signals are affected by pin configuration are
12 For a client device to operate correctly, certain pin controllers must
13 set up certain specific pin configurations. Some client devices need a
14 single static pin configuration, e.g. set up during initialization. Others
21 for client device device tree nodes to map those state names to the pin
24 Note that pin controllers themselves may also be client devices of themselves.
25 For example, a pin controller may set up its own "active" state when the
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| D | cnxt,cx92755-pinctrl.txt | 1 Conexant Digicolor CX92755 General Purpose Pin Mapping
3 This document describes the device tree binding of the pin mapping hardware
7 === Pin Controller Node ===
12 - reg: Base address of the General Purpose Pin Mapping register block and the
15 - #gpio-cells: Must be <2>. The first cell is the pin number and the
28 As a pin controller device, in addition to the required properties, this node
29 should also contain the pin configuration nodes that client devices reference,
34 === Pin Configuration Node ===
36 Each pin configuration node is a sub-node of the pin controller node and is a
37 container of an arbitrary number of subnodes, called pin group nodes in this
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| D | sprd,pinctrl.txt | 1 * Spreadtrum Pin Controller
3 The Spreadtrum pin controller are organized in 3 blocks (types).
9 driving level": One pin can output 3.0v or 1.8v, depending on the
11 select 3.0v, then the pin can output 3.0v. "system control" is used
23 bits in one global control register as one pin, thus we should
24 record every pin's bit offset, bit width and register offset to
25 configure this field (pin).
28 register definition, and each register described one pin is used
29 to configure the pin sleep mode, function select and sleep related
33 PUBCP system, TGLDSP system and AGDSP system. And the pin sleep
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| D | pinctrl.yaml | 7 title: Pin controller device
14 Pin controller devices should contain the pin configuration nodes that client
17 The contents of each of those pin configuration child nodes is defined
18 entirely by the binding for the individual pin controller device. There
20 provides generic helper bindings that the pin controller driver can use.
22 The pin configuration nodes need not be direct children of the pin controller
25 nodes, is again defined entirely by the binding for the individual pin
34 Number of pin control cells in addition to the index within the pin
40 Indicates that the OS can use the boot default pin configuration. This
41 allows using an OS that does not have a driver for the pin controller.
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| D | renesas,rza1-ports.yaml | 7 title: Renesas RZ/A1 combined Pin and GPIO controller
14 The Renesas SoCs of the RZ/A1 family feature a combined Pin and GPIO
16 Pin multiplexing and GPIO configuration is performed on a per-pin basis
20 Up to 8 different alternate function modes exist for each single pin.
47 Each port of the r7s72100 pin controller hardware is itself a GPIO
77 A pin multiplexing sub-node describes how to configure a set of (or a
78 single) pin in some desired alternate function mode.
79 A single sub-node may define several pin configurations.
80 A few alternate function require special pin configuration flags to be
82 The hardware reference manual specifies when a pin function requires
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| D | samsung,pinctrl.yaml | 7 title: Samsung S3C/S5P/Exynos SoC pin controller
15 This is a part of device tree bindings for Samsung S3C/S5P/Exynos SoC pin
18 All the pin controller nodes should be represented in the aliases node using
22 - External GPIO interrupts (see interrupts property in pin controller node);
29 interrupts property in every bank of pin controller with external wake-up
70 Second base address of the pin controller if the specific registers of
71 the pin controller are separated into the different base address.
72 Only certain banks of certain pin controller might need it.
89 Pin banks of the controller are represented by child nodes of the
110 "^(pin-[a-z0-9-]+|[a-z0-9-]+-pin)$":
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| D | samsung,pinctrl-pins-cfg.yaml | 7 title: Samsung S3C/S5P/Exynos SoC pin controller - pins configuration
15 This is a part of device tree bindings for Samsung S3C/S5P/Exynos SoC pin
18 Pins configuration for Samsung S3C/S5P/Exynos SoC pin controller.
21 manual and these values are programmed as-is into the pin pull up/down and
22 driver strength register of the pin-controller.
31 number is one pin. In other cases there is no upper limit.
37 samsung,pin-function:
39 The pin function selection that should be applied on the pins listed in the
40 child node is specified using the "samsung,pin-function" property. The value
43 for the specified pin group. This property is optional in the child node if
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| D | marvell,armada-37xx-pinctrl.txt | 1 * Marvell Armada 37xx SoC pin and gpio controller
3 Each Armada 37xx SoC come with two pin and gpio controller one for the
11 GPIO and pin controller:
18 of the phrase "pin configuration node".
45 - pin 11 (GPIO1-11)
49 - pin 12
53 - pin 13
57 - pin 14
61 - pin 7
65 - pin 6
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| D | brcm,nsp-gpio.txt | 12 Must be two. The first cell is the GPIO pin number (within the
13 controller's pin space) and the second cell is used for the following:
30 Specifies the mapping between gpio controller and pin-controllers pins.
32 1. Phandle of pin-controller.
33 2. GPIO base pin offset.
34 3 Pin-control base pin offset.
35 4. number of gpio pins which are linearly mapped from pin base.
39 The list of pins (within the controller's own pin space) that properties
40 in the node apply to. Pin names are "gpio-<pin>"
43 Disable pin bias
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| D | renesas,rzn1-pinctrl.yaml | 7 title: Renesas RZ/N1 Pin Controller
51 A pin multiplexing sub-node describes how to configure a set of (or a
52 single) pin in some desired alternate function mode.
53 A single sub-node may define several pin configurations.
58 Integer array representing pin number and pin multiplexing
60 When a pin has to be configured in alternate function mode, use
61 this property to identify the pin by its global index, and provide
67 (PIN | MUX_FUNC << 8)
68 where PIN directly corresponds to the pl_gpio pin number and
79 description: Pull up the pin with 50 kOhm
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| D | cortina,gemini-pinctrl.txt | 1 Cortina Systems Gemini pin controller
3 This pin controller is found in the Cortina Systems Gemini SoC family,
4 see further arm/gemini.txt. It is a purely group-based multiplexing pin
7 The pin controller node must be a subnode of the system controller node.
12 Subnodes of the pin controller contain pin control multiplexing set-up
13 and pin configuration of individual pins.
15 Please refer to pinctrl-bindings.txt for generic pin multiplexing nodes
16 and generic pin config nodes.
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| D | sprd,sc9860-pinctrl.txt | 1 * Spreadtrum SC9860 Pin Controller
8 - reg: The register address of pin controller device.
9 - pins : An array of strings, each string containing the name of a pin.
18 - bias-disable: Disable pin bias.
19 - bias-pull-down: Pull down on pin.
20 - bias-pull-up: Pull up on pin. Supported values: 20000 for pull-up resistor
22 - input-enable: Enable pin input.
23 - input-disable: Enable pin output.
24 - output-high: Set the pin as an output level high.
25 - output-low: Set the pin as an output level low.
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| /Documentation/netlink/specs/ |
| D | dpll.yaml | 22 doc: highest prio input pin auto selected by dpll
79 locked on an input pin of type PIN_TYPE_SYNCE_ETH_PORT.
86 locked on an input pin of type PIN_TYPE_SYNCE_ETH_PORT.
114 name: pin-type
116 defines possible types of a pin, valid values for DPLL_A_PIN_TYPE
138 name: pin-direction
140 defines possible direction of a pin, valid values for
145 doc: pin used as a input of a signal
149 doc: pin used to output the signal
153 name: pin-frequency-1-hz
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| /Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/ |
| D | pincfg.txt | 1 * Pin configuration nodes
4 - pio-map : array of pin configurations. Each pin is defined by 6
5 integers. The six numbers are respectively: port, pin, dir,
7 - port : port number of the pin; 0-6 represent port A-G in UM.
8 - pin : pin number in the port.
9 - dir : direction of the pin, should encode as follows:
11 0 = The pin is disabled
12 1 = The pin is an output
13 2 = The pin is an input
14 3 = The pin is I/O
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| /Documentation/devicetree/bindings/sound/ |
| D | realtek,rt5659.yaml | 60 realtek,dmic1-data-pin:
64 - 1 # using IN2N pin as dmic1 data pin
65 - 2 # using GPIO5 pin as dmic1 data pin
66 - 3 # using GPIO9 pin as dmic1 data pin
67 - 4 # using GPIO11 pin as dmic1 data pin
68 description: Specify which pin to be used as DMIC1 data pin.
71 realtek,dmic2-data-pin:
75 - 1 # using IN2P pin as dmic2 data pin
76 - 2 # using GPIO6 pin as dmic2 data pin
77 - 3 # using GPIO10 pin as dmic2 data pin
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| D | rt5668.txt | 15 - realtek,dmic1-data-pin
17 1: using GPIO2 pin as dmic1 data pin
18 2: using GPIO5 pin as dmic1 data pin
20 - realtek,dmic1-clk-pin
21 0: using GPIO1 pin as dmic1 clock pin
22 1: using GPIO3 pin as dmic1 clock pin
28 - realtek,ldo1-en-gpios : The GPIO that controls the CODEC's LDO1_EN pin.
47 realtek,dmic1-data-pin = <1>;
48 realtek,dmic1-clk-pin = <1>;
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| D | realtek,rt5645.yaml | 58 A GPIO spec for the external headphone detect pin. If jd-mode = 0, we
74 realtek,dmic1-data-pin:
75 description: Specify which pin to be used as DMIC1 data pin.
79 - 1 # using IN2P pin as dmic1 data pin
80 - 2 # using GPIO6 pin as dmic1 data pin
81 - 3 # using GPIO10 pin as dmic1 data pin
82 - 4 # using GPIO12 pin as dmic1 data pin
84 realtek,dmic2-data-pin:
85 description: Specify which pin to be used as DMIC2 data pin.
89 - 1 # using IN2N pin as dmic2 data pin
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| D | rt5682.txt | 12 AVDD pin
15 bias through the MICVDD pin. Either MICVDD or VBAT should be present.
18 VBAT pin. Either MICVDD or VBAT should be present.
21 pin.
24 and charge pump through the LDO1_IN pin.
30 - realtek,dmic1-data-pin
32 1: using GPIO2 pin as dmic1 data pin
33 2: using GPIO5 pin as dmic1 data pin
35 - realtek,dmic1-clk-pin
36 0: using GPIO1 pin as dmic1 clock pin
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| D | realtek,rt5682s.yaml | 30 realtek,dmic1-data-pin:
34 - 1 # using GPIO2 pin as dmic1 data pin
35 - 2 # using GPIO5 pin as dmic1 data pin
37 Specify which GPIO pin be used as DMIC1 data pin.
39 realtek,dmic1-clk-pin:
43 - 1 # using GPIO1 pin as dmic1 clock pin
44 - 2 # using GPIO3 pin as dmic1 clock pin
46 Specify which GPIO pin be used as DMIC1 clk pin.
58 The GPIO that controls the CODEC's LDO1_EN pin.
97 description: Regulator supplying analog power through the AVDD pin.
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| D | rt5665.txt | 21 - realtek,dmic1-data-pin
23 1: using GPIO4 pin as dmic1 data pin
24 2: using IN2N pin as dmic2 data pin
26 - realtek,dmic2-data-pin
28 1: using GPIO5 pin as dmic2 data pin
29 2: using IN2P pin as dmic2 data pin
35 - realtek,ldo1-en-gpios : The GPIO that controls the CODEC's LDO1_EN pin.
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| /Documentation/driver-api/ |
| D | dpll.rst | 46 Pin object
49 A pin is amorphic object which represents either input or output, it
54 Pin's properties, capabilities and status is provided to the user in
58 Configuration of a pin can be changed by `do` request of netlink
60 Pin handle is a ``DPLL_A_PIN_ID``, it shall be provided to get or set
61 configuration of particular pin in the system. It can be obtained with
63 request, where user provides attributes that result in single pin match.
65 Pin selection
68 In general, selected pin (the one which signal is driving the dpll
70 one pin shall be in ``DPLL_PIN_STATE_CONNECTED`` state for any dpll
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| D | pin-control.rst | 2 PINCTRL (PIN CONTROL) subsystem
5 This document outlines the pin control subsystem in Linux
22 - A PIN CONTROLLER is a piece of hardware, usually a set of registers, that
28 in the range 0..maxpin. This numberspace is local to each PIN CONTROLLER, so
29 there may be several such number spaces in a system. This pin space may
31 pin exists.
33 When a PIN CONTROLLER is instantiated, it will register a descriptor to the
34 pin control framework, and this descriptor contains an array of pin descriptors
35 describing the pins handled by this specific pin controller.
37 Here is an example of a PGA (Pin Grid Array) chip seen from underneath::
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| /Documentation/driver-api/media/drivers/ |
| D | saa7134-devel.rst | 34 - GP27 MDT2005 PB4 pin 10
35 - GP26 MDT2005 PB3 pin 9
36 - GP25 MDT2005 PB2 pin 8
37 - GP23 MDT2005 PB1 pin 7
38 - GP22 MDT2005 PB0 pin 6
39 - GP21 MDT2005 PB5 pin 11
40 - GP20 MDT2005 PB6 pin 12
41 - GP19 MDT2005 PB7 pin 13
42 - nc MDT2005 PA3 pin 2
43 - Remote MDT2005 PA2 pin 1
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| /Documentation/devicetree/bindings/net/ |
| D | icplus-ip101ag.txt | 4 - IP101GR (32-pin QFN package)
6 - IP101GA (48-pin LQFP package)
10 - IP101A (48-pin LQFP package)
11 - IP101AH (48-pin LQFP package)
13 Optional properties for the IP101GR (32-pin QFN package):
16 pin 21 ("RXER/INTR_32") will output the receive error status.
19 pin 21 ("RXER/INTR_32") will output the interrupt signal.
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