| /Documentation/devicetree/bindings/pinctrl/ |
| D | loongson,ls2k-pinctrl.yaml | 30 'pinmux$':
33 $ref: pinmux-node.yaml#
66 sdio-pinmux {
71 sdio-det-pinmux {
78 pinmux {
85 pinmux {
92 pinmux {
99 pinmux {
106 pinmux {
113 grp0-pinmux {
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| D | nvidia,tegra234-pinmux-aon.yaml | 4 $id: http://devicetree.org/schemas/pinctrl/nvidia,tegra234-pinmux-aon.yaml#
7 title: NVIDIA Tegra234 AON Pinmux Controller
15 const: nvidia,tegra234-pinmux-aon
21 "^pinmux(-[a-z0-9-]+)?$":
26 $ref: nvidia,tegra234-pinmux-common.yaml
67 pinmux@c300000 {
68 compatible = "nvidia,tegra234-pinmux-aon";
74 cec_state: pinmux-cec {
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| D | brcm,ns-pinmux.yaml | 4 $id: http://devicetree.org/schemas/pinctrl/brcm,ns-pinmux.yaml#
23 - brcm,bcm4708-pinmux
24 - brcm,bcm4709-pinmux
25 - brcm,bcm53012-pinmux
37 $ref: pinmux-node.yaml#
61 const: brcm,bcm4708-pinmux
82 compatible = "brcm,bcm4708-pinmux";
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| D | intel,lgm-io.yaml | 7 title: Intel Lightning Mountain SoC pinmux & GPIO controller
13 Pinmux & GPIO controller controls pin multiplexing & configuration including
30 $ref: pinmux-node.yaml#
36 pinmux: true
60 # Pinmux controller node
70 pinmux = <1>,
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| D | nvidia,tegra124-pinmux.yaml | 4 $id: http://devicetree.org/schemas/pinctrl/nvidia,tegra124-pinmux.yaml#
7 title: NVIDIA Tegra124 Pinmux Controller
14 Tegra30 pinctrl binding, as described in nvidia,tegra20-pinmux.yaml and
15 nvidia,tegra30-pinmux.yaml. In fact, this document assumes that binding as a
21 - const: nvidia,tegra124-pinmux
23 - const: nvidia,tegra132-pinmux
24 - const: nvidia,tegra124-pinmux
29 - description: pinmux registers
33 "^pinmux(-[a-z0-9-_]+)?$":
38 $ref: nvidia,tegra-pinmux-common.yaml
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| D | nvidia,tegra210-pinmux.yaml | 4 $id: http://devicetree.org/schemas/pinctrl/nvidia,tegra210-pinmux.yaml#
7 title: NVIDIA Tegra210 Pinmux Controller
15 const: nvidia,tegra210-pinmux
20 - description: PINMUX_AUX_* registers (pinmux)
23 "^pinmux(-[a-z0-9-_]+)?$":
28 $ref: nvidia,tegra-pinmux-common.yaml
120 pinmux: pinmux@70000800 {
121 compatible = "nvidia,tegra210-pinmux";
128 state_boot: pinmux {
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| D | pinmux-node.yaml | 4 $id: http://devicetree.org/schemas/pinctrl/pinmux-node.yaml#
85 For cases like this, the pin controller driver may use the pinmux helper
87 in a pinmux group. A pinmux group consists of the pin identifier and mux
90 The pinmux property accepts an array of pinmux groups, each of them describing
95 pinmux = <PINMUX_GROUP>, <PINMUX_GROUP>, ...;
101 together in a pinmux group.
122 this, "pins" or "pinmux" has to be specified)
124 pinmux:
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| D | nvidia,tegra194-pinmux.yaml | 4 $id: http://devicetree.org/schemas/pinctrl/nvidia,tegra194-pinmux.yaml#
7 title: NVIDIA Tegra194 Pinmux Controller
16 - nvidia,tegra194-pinmux
17 - nvidia,tegra194-pinmux-aon
21 - description: pinmux registers
24 "^pinmux(-[a-z0-9-_]+)?$":
29 $ref: nvidia,tegra-pinmux-common.yaml
62 const: nvidia,tegra194-pinmux
65 "^pinmux(-[a-z0-9-_]+)?$":
216 const: nvidia,tegra194-pinmux-aon
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| D | renesas,rzn1-pinctrl.yaml | 48 - $ref: pinmux-node.yaml#
56 pinmux:
65 same argument list of a single "pinmux" property.
66 Integers values in the "pinmux" argument list are assembled as:
87 - pinmux
111 pinmux = <
121 pinmux = <RZN1_PINMUX(103, RZN1_FUNC_UART0_I)>;
124 pinmux = <RZN1_PINMUX(104, RZN1_FUNC_UART0_I)>;
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| D | nxp,s32g2-siul2-pinctrl.yaml | 15 S32G2 pinmux is implemented in SIUL2 (System Integration Unit Lite2),
21 IMCR registers need to be revealed for kernel to configure pinmux.
57 - $ref: pinmux-node.yaml#
72 pinmux:
74 An integer array for representing pinmux configurations of
77 calculated as: pinmux = (PIN_ID << 4 | SSS)
111 pinmux = <0x2b0>;
117 pinmux = <0x2c2>;
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| D | nvidia,tegra234-pinmux.yaml | 4 $id: http://devicetree.org/schemas/pinctrl/nvidia,tegra234-pinmux.yaml#
7 title: NVIDIA Tegra234 Pinmux Controller
15 const: nvidia,tegra234-pinmux
21 "^pinmux(-[a-z0-9-]+)?$":
26 $ref: nvidia,tegra234-pinmux-common.yaml
124 pinmux@2430000 {
125 compatible = "nvidia,tegra234-pinmux";
131 pex_rst_c5_out_state: pinmux-pex-rst-c5-out {
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| D | mediatek,mt8195-pinctrl.yaml | 80 pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
86 pinmux = <PINMUX_GPIO8__FUNC_SDA0>;
90 $ref: pinmux-node.yaml
93 pinmux:
135 pinmux = <PINMUX_GPIO8__FUNC_SDA0>;
147 pinmux = <PINMUX_GPIO8__FUNC_SDA0>;
183 pinmux = <PINMUX_GPIO8__FUNC_SDA0>;
195 pinmux = <PINMUX_GPIO8__FUNC_SDA0>;
216 - pinmux
260 pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
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| D | mediatek,mt65xx-pinctrl.yaml | 34 Specify the subnodes are using numbered pinmux to specify pins. (UNUSED)
89 pinmux:
125 - pinmux
163 pinmux = <MT8135_PIN_100_SDA0__FUNC_SDA0>,
171 pinmux = <MT8135_PIN_195_SDA1__FUNC_SDA1>,
179 pinmux = <MT8135_PIN_193_SDA2__FUNC_SDA2>;
184 pinmux = <MT8135_PIN_49_WATCHDOG__FUNC_GPIO49>;
191 pinmux = <MT8135_PIN_40_DAC_CLK__FUNC_GPIO40>,
197 pinmux = <MT8135_PIN_35_SCL3__FUNC_SCL3>,
204 pinmux = <MT8135_PIN_57_JTCK__FUNC_GPIO57>,
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| D | sophgo,cv1800-pinctrl.yaml | 55 - $ref: pinmux-node.yaml#
58 pinmux:
87 - pinmux
111 pinmux = <PINMUX(PIN_UART0_TX, 0)>,
112 <PINMUX(PIN_UART0_RX, 0)>;
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| D | atmel,at91-pio4-pinctrl.txt | 28 pinmux = <PIN_NUMBER_PINMUX>;
33 - pinmux: integer array. Each integer represents a pin number plus mux and
67 pinmux = <PIN_PD21__TWD0>,
73 pinmux = <PIN_PB0>,
81 pinmux = <PIN_PA28__SDMMC1_CMD>,
90 pinmux = <PIN_PA22__SDMMC1_CK>,
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| D | nvidia,tegra114-pinmux.yaml | 4 $id: http://devicetree.org/schemas/pinctrl/nvidia,tegra114-pinmux.yaml#
7 title: NVIDIA Tegra114 pinmux Controller
15 const: nvidia,tegra114-pinmux
23 "^pinmux(-[a-z0-9-_]+)?$":
28 $ref: nvidia,tegra-pinmux-common.yaml
125 pinmux@70000868 {
126 compatible = "nvidia,tegra114-pinmux";
128 <0x70003000 0x40c>; /* PinMux registers */
130 pinmux {
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| D | mediatek,mt8186-pinctrl.yaml | 87 pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
93 pinmux = <PINMUX_GPIO128__FUNC_SDA0>;
97 $ref: pinmux-node.yaml
100 pinmux:
139 pinmux = <PINMUX_GPIO128__FUNC_SDA0>;
151 pinmux = <PINMUX_GPIO128__FUNC_SDA0>;
187 pinmux = <PINMUX_GPIO128__FUNC_SDA0>;
208 - pinmux
249 pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
256 pinmux = <PINMUX_GPIO0__FUNC_SPI0_CLK_B>,
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| D | brcm,nsp-pinmux.txt | 8 Must be "brcm,nsp-pinmux"
26 pinmux: pinmux@1803f1c0 {
27 compatible = "brcm,nsp-pinmux";
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| D | renesas,rza1-ports.yaml | 74 - $ref: pinmux-node.yaml#
94 pinmux:
103 same argument list of a single "pinmux" property.
108 Integers values in "pinmux" argument list are assembled as:
115 - pinmux
150 pinmux = <RZA1_PINMUX(3, 0, 6)>, <RZA1_PINMUX(3, 2, 4)>;
162 pinmux = <RZA1_PINMUX(1, 4, 1)>, <RZA1_PINMUX(1, 5, 1)>;
176 pinmux = <RZA1_PINMUX(4, 0, 2)>;
186 pinmux = <RZA1_PINMUX(4, 1, 1)>;
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| D | nvidia,tegra20-pinmux.yaml | 4 $id: http://devicetree.org/schemas/pinctrl/nvidia,tegra20-pinmux.yaml#
7 title: NVIDIA Tegra20 Pinmux Controller
15 const: nvidia,tegra20-pinmux
25 "^pinmux(-[a-z0-9-_]+)?$":
30 $ref: nvidia,tegra-pinmux-common.yaml
95 compatible = "nvidia,tegra20-pinmux";
101 pinmux {
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| D | pinctrl_spear.txt | 1 ST Microelectronics, SPEAr pinmux controller
4 - compatible : "st,spear300-pinmux"
5 : "st,spear310-pinmux"
6 : "st,spear320-pinmux"
7 : "st,spear1310-pinmux"
8 : "st,spear1340-pinmux"
10 - st,pinmux-mode: Mandatory for SPEAr300 and SPEAr320 and invalid for others.
35 SPEAr's pinmux nodes act as a container for an arbitrary number of subnodes. Each
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| D | renesas,rza2-pinctrl.yaml | 45 - $ref: pinmux-node.yaml#
53 The values for the pinmux properties are a combination of port name,
61 pinmux:
68 - pinmux
95 pinmux = <RZA2_PINMUX(PORT9, 0, 4)>, /* TxD4 */
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| D | brcm,cygnus-pinmux.txt | 9 Must be "brcm,cygnus-pinmux"
28 pinmux: pinmux@0301d0c8 {
29 compatible = "brcm,cygnus-pinmux";
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| D | mediatek,mt6795-pinctrl.yaml | 75 pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
81 pinmux = <PINMUX_GPIO45__FUNC_SDA0>;
85 $ref: pinmux-node.yaml
88 pinmux:
156 - pinmux
197 pinmux = <PINMUX_GPIO45__FUNC_SDA0>,
204 pinmux = <PINMUX_GPIO154__FUNC_MSDC0_DAT0>,
218 pinmux = <PINMUX_GPIO163__FUNC_MSDC0_CLK>;
223 pinmux = <PINMUX_GPIO165__FUNC_MSDC0_RSTB>;
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| D | nvidia,tegra30-pinmux.yaml | 4 $id: http://devicetree.org/schemas/pinctrl/nvidia,tegra30-pinmux.yaml#
7 title: NVIDIA Tegra30 pinmux Controller
15 const: nvidia,tegra30-pinmux
23 "^pinmux(-[a-z0-9-_]+)?$":
28 $ref: nvidia,tegra-pinmux-common.yaml
146 compatible = "nvidia,tegra30-pinmux";
150 pinmux {
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