Searched full:qup (Results 1 – 14 of 14) sorted by relevance
| /Documentation/devicetree/bindings/i2c/ |
| D | qcom,i2c-geni-qcom.yaml | 7 title: Qualcomm Geni based QUP I2C Controller
101 - const: qup-core
102 - const: qup-config
116 - const: qup-core
117 - const: qup-config
118 - const: qup-memory
142 interconnect-names = "qup-core", "qup-config", "qup-memory";
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| D | qcom,i2c-qup.yaml | 4 $id: http://devicetree.org/schemas/i2c/qcom,i2c-qup.yaml#
7 title: Qualcomm Universal Peripheral (QUP) I2C controller
20 - qcom,i2c-qup-v1.1.1 # for 8660, 8960 and 8064
21 - qcom,i2c-qup-v2.1.1 # for 8974 v1
22 - qcom,i2c-qup-v2.2.1 # for 8974 v2 and later
73 compatible = "qcom,i2c-qup-v2.2.1";
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| /Documentation/devicetree/bindings/spi/ |
| D | qcom,spi-qup.yaml | 4 $id: http://devicetree.org/schemas/spi/qcom,spi-qup.yaml#
7 title: Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI)
15 The QUP core is an AHB slave that provides a common data path (an output FIFO
27 - qcom,spi-qup-v1.1.1 # for 8660, 8960 and 8064
28 - qcom,spi-qup-v2.1.1 # for 8974 and later
29 - qcom,spi-qup-v2.2.1 # for 8974 v2 and later
78 compatible = "qcom,spi-qup-v2.2.1";
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| D | qcom,spi-geni-qcom.yaml | 7 title: GENI based Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI)
15 The QUP v3 core is a GENI based AHB slave that provides a common data path
23 Peripharal. Please refer GENI based QUP wrapper controller node bindings
54 - const: qup-core
55 - const: qup-config
56 - const: qup-memory
99 interconnect-names = "qup-core", "qup-config";
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| /Documentation/devicetree/bindings/soc/qcom/ |
| D | qcom,geni-se.yaml | 7 title: GENI Serial Engine QUP Wrapper Controller
13 Generic Interface (GENI) based Qualcomm Universal Peripheral (QUP) wrapper
15 like UART, SPI, I2C, I3C, etc. A single QUP module can provide upto 8 Serial
16 Interfaces, using its internal Serial Engines. The GENI Serial Engine QUP
23 - qcom,geni-se-qup
27 description: QUP wrapper common register address and length.
50 const: qup-core
130 compatible = "qcom,geni-se-qup";
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| D | qcom,gsbi.yaml | 45 CRCI MUX value for QUP CRCI ports. Please reference
70 $ref: /schemas/spi/qcom,spi-qup.yaml#
74 $ref: /schemas/i2c/qcom,i2c-qup.yaml#
119 compatible = "qcom,i2c-qup-v1.1.1";
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| /Documentation/devicetree/bindings/serial/ |
| D | qcom,serial-geni-qcom.yaml | 7 title: Qualcomm Geni based QUP UART interface
33 - const: qup-core
34 - const: qup-config
84 interconnect-names = "qup-core", "qup-config";
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| /Documentation/devicetree/bindings/interconnect/ |
| D | qcom,qcm2290.yaml | 43 - qcom,qcm2290-qup-virt
67 qup_virt: interconnect-qup {
68 compatible = "qcom,qcm2290-qup-virt";
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| D | qcom,rpmh.yaml | 37 - qcom,sc7180-qup-virt
48 - qcom,sc8180x-qup-virt
91 - qcom,sm8250-qup-virt
118 - qcom,sc8180x-qup-virt
120 - qcom,sm8250-qup-virt
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | qcom,sdm670-tlmm.yaml | 107 qup-i2c9-state {
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| D | qcom,sa8775p-tlmm.yaml | 120 qup-uart10-state {
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| D | qcom,sc7180-pinctrl.yaml | 133 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state {
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| D | qcom,sc7280-pinctrl.yaml | 124 qup_uart5_default: qup-uart5-state {
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| D | qcom,sm8150-pinctrl.yaml | 130 qup-spi0-default-state {
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