Searched full:rmii (Results 1 – 25 of 47) sorted by relevance
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| /Documentation/devicetree/bindings/net/ |
| D | mediatek-dwmac.yaml | 54 - description: RMII reference clock provided by MAC
81 For MT2712 RMII/MII interface, Allowed value need to be a multiple of 550,
83 For MT8188/MT8195 RGMII/RMII/MII interface, Allowed value need to be a multiple of 290,
91 For MT2712 RMII/MII interface, Allowed value need to be a multiple of 550,
93 For MT8188/MT8195 RGMII/RMII/MII interface, Allowed value need to be a multiple
96 mediatek,rmii-rxc:
99 If present, indicates that the RMII reference clock, which is from external
102 mediatek,rmii-clk-from-mac:
105 If present, indicates that MAC provides the RMII reference clock, which
114 which is from external PHYs in RMII case, and it rarely happen.
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| D | micrel.txt | 23 - micrel,rmii-reference-clock-select-25-mhz: RMII Reference Clock Select
26 Setting the RMII Reference Clock Select bit enables 25 MHz rather
31 Specifically, a clock reference ("rmii-ref" below) is always needed to
37 - KSZ8021, KSZ8031, KSZ8081, KSZ8091: "rmii-ref": The RMII reference
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| D | nxp,tja11xx.yaml | 49 nxp,rmii-refclk-in:
53 in RMII mode. This clock signal is provided by the PHY and is
60 interface reference clock input when RMII mode enabled.
62 reference clock output when RMII mode enabled.
94 nxp,rmii-refclk-in;
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| D | ti,dp83822.yaml | 18 connect to a MAC through a standard MII, RMII, or RGMII interface
83 ti,rmii-mode:
85 If present, select the RMII operation mode. Two modes are
87 - RMII master, where the PHY outputs a 50MHz reference clock which can
89 - RMII slave, where the PHY expects a 50MHz reference clock input
91 The RMII operation mode can also be configured by its straps.
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| D | cpsw-phy-sel.txt | 13 -rmii-clock-ext : If present, the driver will configure the RMII
29 rmii-clock-ext;
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| D | actions,owl-emac.yaml | 14 It provides the RMII and SMII interfaces and is compliant with the
44 - const: rmii
81 clock-names = "eth", "rmii";
83 phy-mode = "rmii";
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| D | lpc-eth.txt | 10 absent, "rmii" is assumed.
26 phy-mode = "rmii";
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| D | faraday,ftgmac100.yaml | 36 - description: RMII RCLK gate for AST2500/2600
47 - rmii
54 rmii (100bT) but kept as a separate property in case NC-SI grows support
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| D | mediatek,star-emac.yaml | 51 mediatek,rmii-rxc:
54 If present, indicates that the RMII reference clock, which is from external
97 phy-mode = "rmii";
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| D | davinci_emac.txt | 23 - ti,davinci-rmii-en: 1 byte, 1 means use RMII
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| D | loongson,ls1c-emac.yaml | 22 - RMII interface
66 - rmii
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| D | adi,adin.yaml | 35 When operating in RMII mode, this option configures the FIFO depth.
77 phy-mode = "rmii";
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| D | sunplus,sp7021-emac.yaml | 116 phy-mode = "rmii";
124 phy-mode = "rmii";
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| D | vertexcom-mse102x.yaml | 14 They can be connected either via RGMII, RMII or SPI to a host CPU.
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| D | lantiq,etop-xway.yaml | 67 phy-mode = "rmii";
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| /Documentation/devicetree/bindings/net/dsa/ |
| D | microchip,ksz.yaml | 70 MII / RMII (except TX_CLK/REFCLKI, COL and CRS) and CLKO_25_125 lines.
105 microchip,rmii-clk-internal:
109 can select between internal and external RMII reference
111 the RMII of ksz88x3 is provided by the ksz88x3 internally
115 If microchip,rmii-clk-internal is set, ksz88x3 will provide
116 rmii reference clock internally, otherwise reference clock
119 microchip,rmii-clk-internal: [ethernet]
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| D | lan9303.txt | 31 fixed-link { /* RMII fixed link to LAN9303 */
47 port@0 { /* RMII fixed link to master */
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| D | arrow,xrs700x.yaml | 18 RGMII ports and one RMII port and are managed via i2c or mdio.
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| /Documentation/devicetree/bindings/clock/ |
| D | starfive,jh7110-aoncrg.yaml | 23 - description: GMAC0 RMII reference or GMAC0 RGMII RX
30 - description: GMAC0 RMII reference or GMAC0 RGMII RX
38 - description: GMAC0 RMII reference
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| D | starfive,jh7110-syscrg.yaml | 23 - description: GMAC1 RMII reference or GMAC1 RGMII RX
36 - description: GMAC1 RMII reference
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| D | starfive,jh7100-clkgen.yaml | 24 - description: RMII reference clock (50 MHz)
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| /Documentation/devicetree/bindings/phy/ |
| D | ti,phy-gmii-sel.yaml | 15 two 10/100/1000 Ethernet ports with selectable G/MII, RMII, and RGMII interfaces.
31 | | | RMII <------->
154 - RMII refclk mode
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| /Documentation/devicetree/bindings/net/pcs/ |
| D | renesas,rzn1-miic.yaml | 14 responsible to do MII passthrough or convert it to RMII/RGMII.
36 - description: RMII reference clock
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| /Documentation/networking/dsa/ |
| D | sja1105.rst | 329 RMII PHY role and out-of-band signaling
332 In the RMII spec, the 50 MHz clock signals are either driven by the MAC or by
337 On the other hand, the SJA1105 is only binary configurable - when in the RMII
339 happening it must be put in RMII PHY role.
341 In the RMII spec, the PHY can transmit extra out-of-band signals via RXD[1:0].
344 mechanism defined by the RMII spec.
346 clock signal, inevitably an RMII PHY-to-PHY connection is created. The SJA1105
355 The take-away is that in RMII mode, the SJA1105 must be let to drive the
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| D | lan9303.rst | 6 the two external ethernet ports. The third port is an RMII/MII interface to a
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