Home
last modified time | relevance | path

Searched full:rtc (Results 1 – 25 of 200) sorted by relevance

12345678

/Documentation/ABI/testing/
Dsysfs-class-rtc1 What: /sys/class/rtc/
4 Contact: linux-rtc@vger.kernel.org
6 The rtc/ class subdirectory belongs to the RTC subsystem.
8 What: /sys/class/rtc/rtcX/
11 Contact: linux-rtc@vger.kernel.org
13 The /sys/class/rtc/rtc{0,1,2,3,...} directories correspond
14 to each RTC device.
16 What: /sys/class/rtc/rtcX/date
19 Contact: linux-rtc@vger.kernel.org
21 (RO) RTC-provided date in YYYY-MM-DD format
[all …]
/Documentation/devicetree/bindings/rtc/
Dallwinner,sun6i-a31-rtc.yaml4 $id: http://devicetree.org/schemas/rtc/allwinner,sun6i-a31-rtc.yaml#
7 title: Allwinner A31 RTC
20 - allwinner,sun6i-a31-rtc
21 - allwinner,sun8i-a23-rtc
22 - allwinner,sun8i-h3-rtc
23 - allwinner,sun8i-r40-rtc
24 - allwinner,sun8i-v3-rtc
25 - allwinner,sun50i-h5-rtc
26 - allwinner,sun50i-h6-rtc
27 - allwinner,sun50i-h616-rtc
[all …]
Dingenic,rtc.yaml4 $id: http://devicetree.org/schemas/rtc/ingenic,rtc.yaml#
13 - $ref: rtc.yaml#
20 - ingenic,jz4770-rtc
21 - ingenic,jz4780-rtc
30 - ingenic,jz4740-rtc
31 - ingenic,jz4760-rtc
33 - const: ingenic,jz4725b-rtc
34 - const: ingenic,jz4740-rtc
37 - ingenic,jz4770-rtc
38 - ingenic,jz4780-rtc
[all …]
Dmoxa,moxart-rtc.txt5 - compatible : Should be "moxa,moxart-rtc"
6 - rtc-sclk-gpios : RTC sclk gpio, with zero flags
7 - rtc-data-gpios : RTC data gpio, with zero flags
8 - rtc-reset-gpios : RTC reset gpio, with zero flags
12 rtc: rtc {
13 compatible = "moxa,moxart-rtc";
14 rtc-sclk-gpios = <&gpio 5 0>;
15 rtc-data-gpios = <&gpio 6 0>;
16 rtc-reset-gpios = <&gpio 7 0>;
Ds3c-rtc.yaml4 $id: http://devicetree.org/schemas/rtc/s3c-rtc.yaml#
16 - samsung,s3c2410-rtc
17 - samsung,s3c2416-rtc
18 - samsung,s3c2443-rtc
19 - samsung,s3c6410-rtc
22 - samsung,exynos7-rtc
23 - samsung,exynos850-rtc
24 - const: samsung,s3c6410-rtc
25 - const: samsung,exynos3250-rtc
33 Must contain a list of phandle and clock specifier for the rtc
[all …]
Datmel,at91rm9200-rtc.yaml4 $id: http://devicetree.org/schemas/rtc/atmel,at91rm9200-rtc.yaml#
7 title: Atmel AT91 RTC
10 - $ref: rtc.yaml#
19 - atmel,at91rm9200-rtc
20 - atmel,at91sam9x5-rtc
21 - atmel,sama5d4-rtc
22 - atmel,sama5d2-rtc
23 - microchip,sam9x60-rtc
24 - microchip,sama7g5-rtc
26 - const: microchip,sam9x7-rtc
[all …]
Dnvidia,tegra20-rtc.yaml4 $id: http://devicetree.org/schemas/rtc/nvidia,tegra20-rtc.yaml#
14 The Tegra RTC maintains seconds and milliseconds counters, and five
21 - const: nvidia,tegra20-rtc
24 - nvidia,tegra30-rtc
25 - nvidia,tegra114-rtc
26 - nvidia,tegra124-rtc
27 - nvidia,tegra210-rtc
28 - nvidia,tegra186-rtc
29 - nvidia,tegra194-rtc
30 - nvidia,tegra234-rtc
[all …]
Dloongson,rtc.yaml4 $id: http://devicetree.org/schemas/rtc/loongson,rtc.yaml#
11 counter) as the RTC.
17 - $ref: rtc.yaml#
23 - loongson,ls1b-rtc
24 - loongson,ls1c-rtc
25 - loongson,ls7a-rtc
26 - loongson,ls2k1000-rtc
29 - loongson,ls2k2000-rtc
30 - loongson,ls2k0500-rtc
31 - const: loongson,ls7a-rtc
[all …]
Dmarvell,armada-380-rtc.yaml4 $id: http://devicetree.org/schemas/rtc/marvell,armada-380-rtc.yaml#
7 title: RTC controller for the Armada 38x, 7K and 8K SoCs
13 - $ref: rtc.yaml#
18 - marvell,armada-380-rtc
19 - marvell,armada-8k-rtc
23 - description: RTC base address size
28 - const: rtc
29 - const: rtc-soc
46 rtc@a3800 {
47 compatible = "marvell,armada-380-rtc";
[all …]
Dsa1100-rtc.yaml4 $id: http://devicetree.org/schemas/rtc/sa1100-rtc.yaml#
10 - $ref: rtc.yaml#
20 - mrvl,sa1100-rtc
21 - mrvl,mmp-rtc
37 - const: rtc 1Hz
38 - const: rtc alarm
50 rtc: rtc@d4010000 {
51 compatible = "mrvl,mmp-rtc";
54 interrupt-names = "rtc 1Hz", "rtc alarm";
Dcirrus,ep9301-rtc.yaml4 $id: http://devicetree.org/schemas/rtc/cirrus,ep9301-rtc.yaml#
14 - $ref: rtc.yaml#
19 - const: cirrus,ep9301-rtc
22 - cirrus,ep9302-rtc
23 - cirrus,ep9307-rtc
24 - cirrus,ep9312-rtc
25 - cirrus,ep9315-rtc
26 - const: cirrus,ep9301-rtc
39 rtc@80920000 {
40 compatible = "cirrus,ep9301-rtc";
Dqcom-pm8xxx-rtc.yaml4 $id: http://devicetree.org/schemas/rtc/qcom-pm8xxx-rtc.yaml#
7 title: Qualcomm PM8xxx PMIC RTC device
16 - qcom,pm8058-rtc
17 - qcom,pm8921-rtc
18 - qcom,pm8941-rtc
19 - qcom,pmk8350-rtc
22 - qcom,pm8018-rtc
23 - const: qcom,pm8921-rtc
32 - const: rtc
41 Indicates that the setting of RTC time is allowed by the host CPU.
[all …]
Drtc-omap.txt5 - "ti,da830-rtc" - for RTC IP used similar to that on DA8xx SoC family.
6 - "ti,am3352-rtc" - for RTC IP used similar to that on AM335x SoC family.
7 This RTC IP has special WAKE-EN Register to enable
11 - "ti,am4372-rtc" - for RTC IP used similar to that on AM437X SoC family.
12 - reg: Address range of rtc register set
13 - interrupts: rtc timer, alarm interrupts in order
16 - system-power-controller: whether the rtc is controlling the system power
18 - clocks: Any internal or external clocks feeding in to rtc
35 rtc@1c23000 {
36 compatible = "ti,da830-rtc";
Dst,stm32-rtc.yaml4 $id: http://devicetree.org/schemas/rtc/st,stm32-rtc.yaml#
15 - st,stm32-rtc
16 - st,stm32h7-rtc
17 - st,stm32mp1-rtc
18 - st,stm32mp25-rtc
44 domain (RTC registers) write protection.
57 "^rtc-[a-z]+-[0-9]+$":
61 Configuration of STM32 RTC pins description. STM32 RTC is able to output
64 - Alarm out that allow to send a pulse on a pin when alarm A of the RTC
83 const: st,stm32-rtc
[all …]
Dxlnx,zynqmp-rtc.yaml4 $id: http://devicetree.org/schemas/rtc/xlnx,zynqmp-rtc.yaml#
10 RTC controller for the Xilinx Zynq MPSoC Real Time Clock.
11 The RTC controller has separate IRQ lines for seconds and alarm.
17 - $ref: rtc.yaml#
22 - const: xlnx,zynqmp-rtc
25 - xlnx,versal-rtc
26 - xlnx,versal-net-rtc
27 - const: xlnx,zynqmp-rtc
37 - const: rtc
74 rtc: rtc@ffa60000 {
[all …]
Drtc-mt6397.txt1 Device-Tree bindings for MediaTek PMIC based RTC
3 MediaTek PMIC based RTC is an independent function of MediaTek PMIC that works
4 as a type of multi-function device (MFD). The RTC can be configured and set up
16 "mediatek,mt6323-rtc": for MT6323 PMIC
17 "mediatek,mt6358-rtc": for MT6358 PMIC
18 "mediatek,mt6366-rtc", "mediatek,mt6358-rtc": for MT6366 PMIC
19 "mediatek,mt6397-rtc": for MT6397 PMIC
28 rtc {
29 compatible = "mediatek,mt6323-rtc";
Dmediatek,mt7622-rtc.yaml4 $id: http://devicetree.org/schemas/rtc/mediatek,mt7622-rtc.yaml#
7 title: MediaTek MT7622 on-SoC RTC
10 - $ref: rtc.yaml#
18 - const: mediatek,mt7622-rtc
19 - const: mediatek,soc-rtc
31 const: rtc
46 rtc@10212800 {
47 compatible = "mediatek,mt7622-rtc", "mediatek,soc-rtc";
51 clock-names = "rtc";
Dtrivial-rtc.yaml4 $id: http://devicetree.org/schemas/rtc/trivial-rtc.yaml#
13 This is a list of trivial RTC devices that have simple device tree
18 - $ref: rtc.yaml#
28 - aspeed,ast2400-rtc
30 - aspeed,ast2500-rtc
32 - aspeed,ast2600-rtc
34 - cnxt,cx92755-rtc
35 # I2C, 32-Bit Binary Counter Watchdog RTC with Trickle Charger and Reset Input/Output
39 # Extremely Accurate I²C RTC with Integrated Crystal and SRAM
43 # EM Microelectronic EM3027 RTC
[all …]
Dallwinner,sun4i-a10-rtc.yaml4 $id: http://devicetree.org/schemas/rtc/allwinner,sun4i-a10-rtc.yaml#
7 title: Allwinner A10 RTC
10 - $ref: rtc.yaml#
19 - allwinner,sun4i-a10-rtc
20 - allwinner,sun7i-a20-rtc
37 rtc: rtc@1c20d00 {
38 compatible = "allwinner,sun4i-a10-rtc";
Dnxp,lpc1788-rtc.yaml4 $id: http://devicetree.org/schemas/rtc/nxp,lpc1788-rtc.yaml#
10 The LPC1788 RTC provides calendar and clock functionality
17 - $ref: rtc.yaml#
21 const: nxp,lpc1788-rtc
28 - description: RTC clock
33 - const: rtc
52 rtc@40046000 {
53 compatible = "nxp,lpc1788-rtc";
56 clock-names = "rtc", "reg";
Dfsl,stmp3xxx-rtc.yaml4 $id: http://devicetree.org/schemas/rtc/fsl,stmp3xxx-rtc.yaml#
13 - $ref: rtc.yaml#
20 - fsl,imx28-rtc
21 - fsl,imx23-rtc
22 - const: fsl,stmp3xxx-rtc
23 - const: fsl,stmp3xxx-rtc
47 rtc@80056000 {
48 compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc";
Damlogic,meson6-rtc.yaml4 $id: http://devicetree.org/schemas/rtc/amlogic,meson6-rtc.yaml#
7 title: Amlogic Meson6, Meson8, Meson8b and Meson8m2 RTC
14 - $ref: rtc.yaml#
21 - amlogic,meson6-rtc
22 - amlogic,meson8-rtc
23 - amlogic,meson8b-rtc
24 - amlogic,meson8m2-rtc
50 rtc: rtc@740 {
51 compatible = "amlogic,meson6-rtc";
Dmicrochip,mfps-rtc.yaml4 $id: http://devicetree.org/schemas/rtc/microchip,mfps-rtc.yaml#
8 title: Microchip PolarFire Soc (MPFS) RTC
11 - $ref: rtc.yaml#
20 - microchip,mpfs-rtc
31 to that of the RTC's count register.
39 strobe (typically 1 Hz) for the calendar counter. By default, the rtc
45 - const: rtc
60 rtc@20124000 {
61 compatible = "microchip,mpfs-rtc";
64 clock-names = "rtc", "rtcref";
Drtc-mxc.yaml4 $id: http://devicetree.org/schemas/rtc/rtc-mxc.yaml#
10 - $ref: rtc.yaml#
18 - fsl,imx1-rtc
19 - fsl,imx21-rtc
30 - description: the SoC RTC clock
50 rtc@10007000 {
51 compatible = "fsl,imx21-rtc";
/Documentation/admin-guide/
Drtc.rst2 Real Time Clock (RTC) Drivers for Linux
16 Linux has two largely-compatible userspace RTC API families you may
19 * /dev/rtc ... is the RTC provided by PC compatible systems,
23 supported by a wide variety of RTC chips on all systems.
27 RTCs use the same API to make requests in both RTC frameworks (using
29 same functionality. For example, not every RTC is hooked up to an
35 Old PC/AT-Compatible driver: /dev/rtc
57 The interrupts are reported via /dev/rtc (major 10, minor 135, read only
62 /proc/driver/rtc if the /proc filesystem was enabled. The driver has
63 built in locking so that only one process is allowed to have the /dev/rtc
[all …]

12345678