| /Documentation/devicetree/bindings/serial/ |
| D | rs485.yaml | 9 description: The RTS signal is capable of automatically controlling line
17 rs485-rts-delay:
21 - description: Delay between rts signal and beginning of data sent in
25 - description: Delay between end of data sent and rts signal in milliseconds.
31 rs485-rts-active-high:
32 description: drive RTS high when sending (this is the default).
35 rs485-rts-active-low:
36 description: drive RTS low when sending (default is high).
40 description: Polarity of receiver enable signal (when separate from RTS).
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| D | serial.yaml | 58 rts-gpios:
62 the UART's RTS line.
68 for RTS/CTS hardware flow control, and that they are available for use
76 cts-rts-swap:
78 description: CTS and RTS pins are swapped.
117 rts-gpios: false
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| D | st,stm32-uart.yaml | 50 # cts-gpios and rts-gpios properties can be used instead of 'uart-has-rtscts'
54 # It should be noted that both cts-gpios/rts-gpios and 'uart-has-rtscts' or
57 rts-gpios: true
89 rts-gpios: false
130 rs485-rts-active-low;
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| D | cirrus,clps711x-uart.txt | 11 - {rts,cts,dtr,dsr,rng,dcd}-gpios: specify a GPIO for RTS/CTS/DTR/DSR/RI/DCD
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| D | 8250_omap.yaml | 67 rts-gpios: true
73 rs485-rts-active-high: true
74 rts-gpio: true
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| D | fsl-mxs-auart.yaml | 54 rts-gpios: true
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| D | 8250.yaml | 190 rts-gpios: true
244 rts-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
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| /Documentation/devicetree/bindings/leds/ |
| D | richtek,rt8515.yaml | 16 RFS and RTS.
39 richtek,rts-ohms:
42 description: The resistance value of the RTS resistor. This
44 for the property torch-max-microamp to work, the RTS resistor
71 is hardwired to the component using the RTS resistor to
73 according to the formula Imax = 5500 / RTS. The lowest
77 current below the hardware limit. This requires the RTS
100 richtek,rts-ohms = <100000>;
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | marvell,armada-370-pinctrl.txt | 24 mpp8 8 gpio, ge0(txd2), uart0(rts), tdm(drx), audio(bclk)
43 mpp22 22 gpo, ge0(txd6), ge1(txd2), uart0(rts)
61 mpp40 40 gpio, dev(ad1), uart1(rts), uart0(rts)
69 mpp48 48 gpio, dev(ad9), uart0(rts), sd0(cmd), sata1(prsnt),
86 mpp58 58 gpio, dev(cs0), uart1(rts), tdm(int), audio(extclk),
87 uart0(rts)
88 mpp59 59 gpo, dev(ale0), uart1(rts), uart0(rts), audio(bclk)
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| D | marvell,kirkwood-pinctrl.txt | 32 mpp8 8 gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
42 mpp15 15 gpio, sdio(d1), uart0(rts), uart1(txd)
70 mpp8 8 gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
80 mpp15 15 gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act)
114 mpp8 8 gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
124 mpp15 15 gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act)
163 mpp8 8 gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
173 mpp15 15 gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act)
226 mpp8 8 gpio, twsi0(sda), uart0(rts), uart1(rts), mii(col),
236 mpp15 15 gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act),
[all …]
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| D | marvell,armada-39x-pinctrl.txt | 22 mpp4 4 gpio, ua1(txd), ua0(rts), smi(mdc)
38 mpp20 20 gpio, sata0(prsnt) [1], ua0(rts), ua1(txd), smi(mdc)
44 mpp25 25 gpio, spi0(cs0), ua0(rts), ua1(txd), sd0(d5), dev(cs0)
59 mpp40 40 gpio, i2c1(sda), ua0(rts), sd0(d2), dev(ad6), ge(rxd3)
61 mpp42 42 gpio, ua1(txd), ua0(rts), dev(ad7)
78 mpp56 56 gpio, ua1(rts), dram(deccerr), spi1(mosi), ua1(txd)
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| D | marvell,armada-38x-pinctrl.txt | 22 mpp4 4 gpio, ge(mdc), ua1(txd), ua0(rts)
38 mpp20 20 gpio, ge0(txclk), ptp(clk), sata0(prsnt), ua0(rts)
43 mpp25 25 gpio, spi0(cs0), ua0(rts), ua1(txd), sd0(d5), dev(cs0)
58 mpp40 40 gpio, i2c1(sda), ge1(rxd3), ua0(rts), sd0(d2), dev(ad6)
60 mpp42 42 gpio, ua1(txd), ua0(rts), dev(ad7)
74 mpp56 56 gpio, ua1(rts), ge(mdc), dram(deccerr), spi1(mosi), ua1(txd)
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| D | marvell,dove-pinctrl.txt | 18 mpp0 0 gpio, pmu, uart2(rts), sdio0(cd), lcd0(pwm), pmu*
21 uart1(rts), pmu*
24 mpp4 4 gpio, pmu, uart3(rts), sdio1(cd), spi1(miso), pmu*
33 mpp12 12 gpio, pmu, uart2(rts), audio0(extclk), sdio1(cd),
39 mpp16 16 gpio, uart3(rts), sdio0(cd), ac97(sdi1), lcd-spi(cs1)
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| D | marvell,armada-xp-pinctrl.txt | 63 mpp41 41 gpio, spi0(cs2), uart2(rts), lcd(vga-vsync), sata1(prsnt),
66 mpp43 43 gpio, uart2(txd), uart0(rts), spi0(cs3), pcie(rstout),
70 mpp45 45 gpio, uart2(rts), uart3(txd), spi0(cs5), sata1(prsnt),
72 mpp46 46 gpio, uart3(rts), uart1(rts), spi0(cs6), sata0(prsnt),
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| D | marvell,orion-pinctrl.txt | 68 mpp19 19 uart1(rts), ge(rxd7), gpio
93 mpp19 19 uart1(rts), ge(rxd7)
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| D | marvell,armada-375-pinctrl.txt | 40 mpp24 24 gpio, led(p0), ge1(rxd0), sd(cmd), uart0(rts)
42 mpp26 26 gpio, pcie0(clkreq), ge1(rxd2), sd(d2), uart1(rts)
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| D | img,pistachio-pinctrl.txt | 194 uart0_rts_cts: uart0-rts-cts {
195 uart0-rts {
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| D | lantiq,pinctrl-xway.txt | 57 spi_cs2, spi_cs3, spi_cs4, spi_cs5, spi_cs6, asc0, asc0 cts rts, stp, nmi,
69 spi_cs6, asc0, asc0 cts rts, stp, nmi, gpt1, gpt2, gpt3, clkout0, clkout1,
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| /Documentation/driver-api/serial/ |
| D | serial-rs485.rst | 20 toggling RTS or DTR signals. That can be used to control external
77 /* Set logical level for RTS pin equal to 1 when sending: */
79 /* or, set logical level for RTS pin equal to 0 when sending: */
82 /* Set logical level for RTS pin equal to 1 after sending: */
84 /* or, set logical level for RTS pin equal to 0 after sending: */
87 /* Set rts delay before send, if needed: */
90 /* Set rts delay after send, if needed: */
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| /Documentation/devicetree/bindings/net/ |
| D | intel,ixp4xx-hss.yaml | 90 rts-gpios:
92 description: Ready To Send (RTS) GPIO line
118 - rts-gpios
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| /Documentation/devicetree/bindings/arm/marvell/ |
| D | cp110-system-controller.txt | 96 mpp5 5 gpio, dev(ad12), au(i2sdi), ge0(rxclk), tdm(intn), mss_uart(txd), uart1(rts), pcie1(clkreq),…
102 mpp11 11 gpio, dev(wen1), ge0(txclkout), spi0(clk), spi1(clk), uart0(rts), led(clk), uart2(txd), sa…
118 …i1(miso), mss_gpio4, ge0(rxd3), spi0(csn4), ge(mdio), sata0(present_act), uart0(rts), rei(in_cp2cp)
134 mpp43 43 gpio, sdio(card_detect), synce1(clk), au(i2sextclk), mss_uart(rxd), spi0(csn0), uart1(rts)…
135 mpp44 44 gpio, ge1(txd2), uart0(rts), ptp(clk_cp2cp)
137 mpp46 46 gpio, ge1(txd1), uart1(rts)
151 mpp60 60 gpio, mss_gpio6, ptp(pulse), tdm(dtx), au(i2smclk), spi0(csn1), uart0(rts), led(data), uar…
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| /Documentation/devicetree/bindings/soc/fsl/cpm_qe/ |
| D | serial.txt | 14 CTS, RTS, DCD, DSR, DTR, and RI.
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| /Documentation/devicetree/bindings/net/bluetooth/ |
| D | nxp,88w8987-bt.yaml | 12 works on standard H4 protocol over 4-wire UART. The RTS and CTS lines
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| /Documentation/hwmon/ |
| D | sbtsi_temp.rst | 38 and physical interface of a typical 8-pin remote temperature sensor (RTS) on
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| /Documentation/devicetree/bindings/gnss/ |
| D | brcm,bcm4751.yaml | 15 bus requires CTS/RTS support. The number of the capsule is more
|