Searched full:receive (Results 1 – 25 of 422) sorted by relevance
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| /Documentation/infiniband/ |
| D | tag_matching.rst | 14 The ordering rules require that when more than one pair of send and receive
16 and the earliest posted-receive is the pair that must be used to satisfy the
23 corresponding matching receive is posted. If a matching receive is posted,
44 There are two types of matching objects used, the posted receive list and the
45 unexpected message list. The application posts receive buffers through calls
46 to the MPI receive routines in the posted receive list and posts send messages
47 using the MPI send routines. The head of the posted receive list may be
50 When send is initiated and arrives at the receive side, if there is no
51 pre-posted receive for this arriving message, it is passed to the software and
54 specified receive buffer. This allows overlapping receive-side MPI tag
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| /Documentation/networking/device_drivers/can/freescale/ |
| D | flexcan.rst | 19 and i.MX53 SOCs) only receive RTR frames if the controller is
30 With the "rx-rtr" private flag the ability to receive RTR frames can
31 be waived at the expense of losing the ability to receive RTR
35 Receive RTR frames. (default)
37 The CAN controller can and will receive RTR frames.
39 On some IP cores the controller cannot receive RTR frames in the
45 Waive ability to receive RTR frames. (not supported on all IP cores)
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| /Documentation/networking/ |
| D | scaling.rst | 17 - RSS: Receive Side Scaling
18 - RPS: Receive Packet Steering
19 - RFS: Receive Flow Steering
20 - Accelerated Receive Flow Steering
24 RSS: Receive Side Scaling
27 Contemporary NICs support multiple receive and transmit descriptor queues
31 of logical flows. Packets for each flow are steered to a separate receive
33 generally known as “Receive-side Scaling” (RSS). The goal of RSS and
42 stores a queue number. The receive queue for a packet is determined
64 can be directed to their own receive queue. Such “n-tuple” filters can
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| D | strparser.rst | 17 The strparser works in one of two modes: receive callback or general
20 In receive callback mode, the strparser is called from the data_ready
33 functions, and a data_ready function for receive callback mode. The
48 socket associated with the stream parser for use with receive
101 maximum messages size is the limit of the receive socket
102 buffer and message timeout is the receive timeout for the socket.
144 zero) and the parser is in receive callback mode, then it will set
156 processing a timeout). In receive callback mode the default
165 by the lock callback. In receive callback mode the default
197 the TCP socket in receive callback mode. The stream parser may
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| D | oa-tc6-framework.rst | 59 receive (RX) chunks. Chunks in both transmit and receive directions may
69 In parallel, receive data chunks are received on MISO. Each receive data
71 The data footer indicates if there is receive frame data present within
184 NORX (Bit 29) - No Receive flag. The SPI host may set this bit to prevent
189 any receive frame data within the current chunk.
200 chunk payload. Note that the receive path is unaffected by
254 host will be sent as multiple receive data chunks. Each receive data
257 location of the receive frame data within the 64 bytes data chunk payload.
284 RCA (Bit 28..24) - Receive Chunks Available. The RCA field indicates to
285 the SPI host the minimum number of additional receive
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| D | tc-queue-filters.rst | 8 to a single queue on both the transmit and receive side.
22 Likewise, on the receive side, the two filters for selecting set of
31 receive queue. The action skbedit queue_mapping for receive queue
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| D | kcm.rst | 9 can efficiently send and receive application protocol messages over TCP using
47 Similarly, in the receive path, messages are constructed on each TCP socket
55 messages on receive as well as other connection specific information for KCM.
63 can be used to send and receive messages from the KCM socket.
98 KCM limits the maximum receive message size to be the size of the receive
105 A timeout may be set for assembling messages on a receive socket. The timeout
106 value is taken from the receive timeout of the attached TCP socket (this is set
189 Disabling receive on KCM socket
193 When receive is disabled, any pending messages in the socket's
194 receive buffer are moved to other sockets. This feature is useful
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| D | mctp.rst | 11 The core code provides a socket-based interface to send and receive MCTP
83 Sockets that receive incoming request packets will bind to a local address,
100 The reference to 'incoming' is important here; a bound socket will only receive
111 receive incoming packets from any locally-connected network. A specific network
112 value will cause the socket to only receive incoming messages from that network.
115 ``MCTP_ADDR_ANY`` configures the socket to receive messages addressed to any
118 The ``smctp_type`` field specifies which message types to receive. Only the
169 implicit local socket address, to allow the socket to receive responses to this
173 Sockets will only receive responses to requests they have sent (with TO=1) and
176 ``recvfrom()``, ``recvmsg()``, ``recv()`` : receive an MCTP message
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| /Documentation/devicetree/bindings/powerpc/fsl/ |
| D | mpic-msgr.txt | 25 - mpic-msgr-receive-mask: Specifies what registers in the containing block
26 are allowed to receive interrupts. The value is a bit mask where a set
27 bit at bit 'n' indicates that message register 'n' can receive interrupts.
50 // Message registers 0 and 2 in this block can receive interrupts on
53 mpic-msgr-receive-mask = <0x5>;
59 // Message registers 0 and 2 in this block can receive interrupts on
62 mpic-msgr-receive-mask = <0x5>;
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| /Documentation/networking/device_drivers/ethernet/microsoft/ |
| D | netvsc.rst | 23 Receive Side Scaling
25 Hyper-V supports receive side scaling. For TCP & UDP, packets can
51 Generic Receive Offload, aka GRO
57 Large Receive Offload (LRO), or Receive Side Coalescing (RSC)
83 Receive Buffer
85 Packets are received into a receive area which is created when device
86 is probed. The receive area is broken into MTU sized chunks and each may
87 contain one or more packets. The number of receive sections may be changed
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | cirrus,clps711x-intc.txt | 25 13: URXINT1 UART1 receive FIFO half full
29 17: SS2RX SSI2 receive FIFO half or greater full
32 29: URXINT2 UART2 receive FIFO half full
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| /Documentation/devicetree/bindings/sound/ |
| D | adi,axi-i2s.txt | 3 The core can be generated with transmit (playback), only receive
15 the core. The core expects two dma channels if both transmit and receive are
17 - dma-names : "tx" for the transmit channel, "rx" for the receive channel.
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| /Documentation/networking/device_drivers/ethernet/huawei/ |
| D | hinic.rst | 21 TCP Transmit Segmentation Offload(TSO), Receive-Side Scaling(RSS) and
22 LRO(Large Receive Offload).
79 accumulated on the CEQ that is configured to receive the CMDQ completion events.
82 Queue Pairs(QPs) - The HW Receive and Send queues for Receiving and Transmitting
108 Rx Queues - Logical Rx Queues that use the HW Receive Queues for receive.
109 The Logical Rx queue is not dependent on the format of the HW Receive Queue.
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| /Documentation/networking/device_drivers/ethernet/altera/ |
| D | altera_tse.rst | 42 The SGDMA supports only a single transmit or receive operation at a time, and
89 4.2. Receive process
91 The driver will post receive buffers to the receive DMA logic during driver
92 initialization. Receive buffers may or may not be queued depending upon the
93 underlying DMA logic (MSGDMA is able queue receive buffers, SGDMA is not able
94 to queue receive buffers to the SGDMA receive logic). When a packet is
95 received, the DMA logic generates an interrupt. The driver handles a receive
96 interrupt by obtaining the DMA receive logic status, reaping receive
97 completions until no more receive completions are available.
102 using NAPI for receive operations. Interrupt mitigation is not yet supported
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| /Documentation/driver-api/serial/ |
| D | serial-rs485.rst | 93 /* Set this flag if you want to receive data even while sending data */
113 has two additional flags and fields for enabling receive and destination
118 - ``SER_RS485_ADDR_RECV``: Receive (filter) address enabled.
122 - ``addr_recv``: Receive address.
125 Once a receive address is set, the communication can occur only with the
127 receiver side to enforce the filtering. Receive address will be cleared
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| /Documentation/networking/device_drivers/ethernet/neterion/ |
| D | s2io.rst | 59 and receive, TSO.
61 c. Multi-buffer receive mode. Scattering of packet across multiple
73 f. Multi-FIFO/Ring. Supports up to 8 transmit queues and receive rings,
87 Number of receive rings
101 Size of each receive ring(in 4K blocks)
164 Receive performance:
176 c. Ensure Receive Checksum offload is enabled. Use "ethtool -K ethX" command to
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| /Documentation/userspace-api/media/rc/ |
| D | lirc-get-rec-mode.rst | 14 LIRC_GET_REC_MODE/LIRC_SET_REC_MODE - Get/set current receive mode.
34 Mode used for receive.
39 Get and set the current receive mode. Only
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| D | lirc-set-rec-carrier.rst | 13 LIRC_SET_REC_CARRIER - Set carrier used to modulate IR receive.
34 Set receive carrier used to modulate IR PWM pulses and spaces.
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| /Documentation/ABI/testing/ |
| D | sysfs-class-net-queues | 7 Receive Packet Steering packet processing flow for this
16 Number of Receive Packet Steering flows being currently
17 processed by this particular network device receive queue.
50 Mask of the receive queue(s) currently enabled to participate
53 number of available receive queue(s) in the network device.
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| /Documentation/devicetree/bindings/net/can/ |
| D | renesas,rcar-canfd.yaml | 122 - description: CAN receive FIFO interrupt
125 - description: CAN0 transmit/receive FIFO receive completion interrupt
128 - description: CAN1 transmit/receive FIFO receive completion interrupt
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| /Documentation/devicetree/bindings/spi/ |
| D | microchip,spi-pic32.txt | 7 of <fault-irq>, <receive-irq>, <transmit-irq>.
18 named "spi-tx" for transmit and named "spi-rx" for receive.
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| /Documentation/core-api/ |
| D | librs.rst | 111 /* Receive data */
113 /* Receive parity */
128 /* Receive data */
130 /* Receive parity */
150 /* Receive data */
152 /* Receive parity */
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| /Documentation/networking/device_drivers/ethernet/intel/ |
| D | fm10k.rst | 84 NOTE: This driver will attempt to use multiple page sized buffers to receive
86 allocating receive packets.
89 Generic Receive Offload, aka GRO
103 Retrieves the receive network flow classification configurations.
109 Configures the receive network flow classification.
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| /Documentation/devicetree/bindings/net/ |
| D | marvell-orion-net.txt | 45 - marvell,rx-queue-size: size of the receive ring buffer.
46 - marvell,rx-sram-addr: address of receive descriptor buffer located in SRAM.
47 - marvell,rx-sram-size: size of receive descriptor buffer located in SRAM.
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| D | davinci_emac.txt | 15 4 sources: <Receive Threshold Interrupt
16 Receive Interrupt
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