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/Documentation/devicetree/bindings/memory-controllers/
Drockchip,rk3399-dmc.yaml69 Configure the SR_IDLE value. Defines the self-refresh idle period in
70 which memories are placed into self-refresh mode if bus is idle for
79 Defines the memory self-refresh and controller clock gating idle period.
80 Memories are placed into self-refresh mode and memory controller clock
89 Defines the self-refresh power down idle period in which memories are
90 placed into self-refresh power down mode if bus is idle for
100 self-refresh mode. The controller, pi, PHY and DRAM clock will be gated
293 Configure the SR_IDLE value in nanoseconds. Defines the self-refresh idle
294 period in which memories are placed into self-refresh mode if bus is idle
300 Defines the memory self-refresh and controller clock gating idle period in nanoseconds.
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/Documentation/ABI/testing/
Dsysfs-driver-hid-picolcd31 Description: Make it possible to adjust defio refresh rate.
33 Reading: returns list of available refresh rates (expressed in Hz),
34 the active refresh rate being enclosed in brackets ('[' and ']')
36 Writing: accepts new refresh rate expressed in integer Hz
Dsysfs-platform-brcmstb-memc6 Self Refresh Power Down (SRPD) inactivity timeout counted in
Dsysfs-bus-rbd81 What: /sys/bus/rbd/devices/<dev-id>/refresh
103 refresh (WO) Writing to this file will reread the image
/Documentation/fb/
Dmodedb.rst23 <xres>x<yres>[M][R][-<bpp>][@<refresh>][i][m][eDd]
24 <name>[-<bpp>][@<refresh>]
26 with <xres>, <yres>, <bpp> and <refresh> decimal numbers and <name> a string.
38 <bpp> and <refresh>, if specified) the timings will be calculated using
91 and coordinated set of standard formats, display refresh rates, and
102 pixelclock, the horizontal sync frequency, or the vertical refresh rate.
137 - acceptable refresh rates are 50, 60, 70 or 85 Hz only
138 - if reduced blanking, the refresh rate must be at 60Hz
162 video=<driver>:<xres>x<yres>[-<bpp>][@refresh]
Duvesafb.rst38 or most optimal resolution/refresh rate for your setup will not work
43 - Adjusting the refresh rate is only possible with a VBE 3.0 compliant
45 compliant, while they simply ignore any refresh rate settings.
121 using this option implies that any refresh rate adjustments will
122 be ignored and the refresh rate will stay at your BIOS default
164 Use the default refresh rate (60 Hz) if set to 1.
179 Uvesafb will set a video mode with the default refresh rate and timings
Dsm501.rst15 "<xres>x<yres>[-<bpp>][@<refresh>]"
Dintel810.rst34 vertical refresh rates if the VESA Generalized Timing Formula is
110 in Hz. You can also use this option to lock your monitor's refresh
173 o. <xres>x<yres>[-<bpp>][@<refresh>]
195 will use 2 MB of System RAM. MTRR support will be enabled. The refresh rate
Dgxfb.rst48 <x>x<y>[-<bpp>][@<refresh>]
Dlxfb.rst49 <x>x<y>[-<bpp>][@<refresh>]
Dpvr2fb.rst33 mode:X default video mode with format [xres]x[yres]-<bpp>@<refresh rate>
Dvesafb.rst96 Refresh rates
100 booting linux. If you are not happy with the 60 Hz refresh rate, you
/Documentation/gpu/amdgpu/display/
Ddc-glossary.rst120 Dynamic Refresh Rate
210 Panel Self Refresh
234 Variable Refresh Rate
/Documentation/devicetree/bindings/auxdisplay/
Dholtek,ht16k33.yaml29 refresh-rate-hz:
67 - refresh-rate-hz
83 refresh-rate-hz = <20>;
/Documentation/devicetree/bindings/memory-controllers/ddr/
Djedec,lpddr3-timings.yaml41 CKE minimum pulse width during SELF REFRESH (low pulse width during
42 SELF REFRESH) in pico seconds.
77 Refresh Cycle time in pico seconds.
122 SELF REFRESH exit to next valid command delay in pico seconds.
Djedec,lpddr3.yaml52 CKE minimum pulse width during SELF REFRESH (low pulse width during
53 SELF REFRESH) in terms of number of clock cycles.
103 Refresh Cycle time in terms of number of clock cycles.
172 SELF REFRESH exit to next valid command delay in terms of number of clock
Djedec,lpddr2-timings.yaml29 CKE minimum pulse width during SELF REFRESH (low pulse width during
30 SELF REFRESH) in pico seconds.
Djedec,lpddr2.yaml116 CKE minimum pulse width during SELF REFRESH (low pulse width during
117 SELF REFRESH) in terms of number of clock cycles. Obtained from device
/Documentation/devicetree/bindings/display/
Dsm501fb.txt15 <xres>x<yres>[-<bpp>][@<refresh>]
/Documentation/devicetree/bindings/watchdog/
Darm,sbsa-gwdt.yaml28 - description: Refresh frame
/Documentation/devicetree/bindings/powerpc/4xx/
Dcpm.txt39 refresh mode and any additional power
/Documentation/devicetree/bindings/arm/
Datmel-sysregs.txt53 Note that they maintain their voltage during Backup/Self-refresh.
/Documentation/devicetree/bindings/display/bridge/
Dti,dlpc3433.yaml21 It supports upto 720p resolution with 60 and 120 Hz refresh
/Documentation/gpu/
Dvkms.rst148 the refresh rate.
171 - Variable refresh rate/freesync support. This probably needs prime buffer
/Documentation/userspace-api/media/v4l/
Dext-ctrls-codec.rst1174 Cyclic intra macroblock refresh. This is the number of continuous
1186 Sets the type of intra refresh. The period to refresh
1189 refresh type is used and it is up to the driver to decide.
1206 Intra macroblock refresh period. This sets the period to refresh
1376 (Instantaneous Decoding Refresh) frames is taken from the GOP_SIZE
1378 Refresh is an I-frame after which no prior frames are referenced.
2131 Sets the refresh period for the golden frame. The period is defined
2135 frame refresh period is set as 4, the frames 0, 4, 8 etc will be
2533 .. _v4l2-hevc-refresh-type:
2539 Selects refresh type for HEVC encoder.
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