Searched full:scg1 (Results 1 – 5 of 5) sorted by relevance
| /Documentation/devicetree/bindings/clock/ |
| D | imx7ulp-pcc-clock.yaml | 24 A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
95 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
96 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
97 <&scg1 IMX7ULP_CLK_DDR_DIV>,
98 <&scg1 IMX7ULP_CLK_APLL_PFD2>,
99 <&scg1 IMX7ULP_CLK_APLL_PFD1>,
100 <&scg1 IMX7ULP_CLK_APLL_PFD0>,
101 <&scg1 IMX7ULP_CLK_UPLL>,
102 <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
103 <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
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| D | imx7ulp-scg-clock.yaml | 24 A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
42 const: fsl,imx7ulp-scg1
81 compatible = "fsl,imx7ulp-scg1";
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| /Documentation/devicetree/bindings/pwm/ |
| D | imx-tpm-pwm.yaml | 56 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
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| /Documentation/devicetree/bindings/watchdog/ |
| D | fsl-imx7ulp-wdt.yaml | 59 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>;
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| /Documentation/devicetree/bindings/timer/ |
| D | nxp,tpm-timer.yaml | 62 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
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