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/Documentation/devicetree/bindings/i2c/
Di2c-gpio.yaml28 scl-gpios:
30 gpio used for the scl signal, this should be flagged as
40 i2c-gpio,scl-output-only:
41 description: scl as output only
54 description: sda and scl gpio, alternative for {sda,scl}-gpios
63 i2c-gpio,scl-open-drain:
67 GPIO line used for SCL into open drain mode, and that something is not
76 i2c-gpio,scl-has-no-pullup:
78 description: scl is used in a non-compliant way and has no pull-up.
80 with i2c-gpio,scl-open-drain.
[all …]
Di2c-rk3x.yaml81 SCL frequency to use (in Hz). If omitted, 100kHz is used.
83 i2c-scl-rising-time-ns:
86 Number of nanoseconds the SCL signal takes to rise
91 i2c-scl-falling-time-ns:
94 Number of nanoseconds the SCL signal takes to fall
103 (t(f) in the I2C specification). If not specified we will use the SCL
139 i2c-scl-falling-time-ns = <100>;
140 i2c-scl-rising-time-ns = <800>;
Dhisilicon,ascend910-i2c.yaml38 i2c-scl-falling-time-ns:
44 i2c-scl-rising-time-ns:
66 i2c-scl-falling-time-ns = <56>;
68 i2c-scl-rising-time-ns = <56>;
Drenesas,rcar-i2c.yaml94 i2c-scl-falling-time-ns:
97 Number of nanoseconds the SCL signal takes to fall; t(f) in the I2C
100 i2c-scl-internal-delay-ns:
103 Number of nanoseconds the IP core additionally needs to setup SCL.
105 i2c-scl-rising-time-ns:
108 Number of nanoseconds the SCL signal takes to rise; t(r) in the I2C
163 i2c-scl-internal-delay-ns = <6>;
Dst,sti-i2c.yaml37 st,i2c-min-scl-pulse-width-us:
39 The minimum valid SCL pulse width that is allowed through the
69 st,i2c-min-scl-pulse-width-us = <0>;
Dst,stm32-i2c.yaml25 i2c-scl-rising-time-ns:
28 i2c-scl-falling-time-ns:
188 i2c-scl-rising-time-ns = <185>;
189 i2c-scl-falling-time-ns = <20>;
Dsnps,designware-i2c.yaml78 i2c-scl-falling-time-ns:
80 The property should contain the SCL falling time in nanoseconds.
123 i2c-scl-falling-time-ns = <300>;
Di2c-mt65xx.yaml89 SCL frequency to use (in Hz). If omitted, 100kHz is used.
100 description: Phandle to the regulator providing power to SCL/SDA
Datmel,at91sam-i2c.yaml62 scl-gpios: true
135 scl-gpios = <&pioA 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
Dxlnx,xps-iic-2.00.a.yaml37 Optional I2C SCL clock frequency. If not specified, do not configure
/Documentation/i2c/
Dgpio-fault-injection.rst20 "scl"
23 By reading this file, you get the current state of SCL. By writing, you can
25 "echo 0 > scl" you force SCL low and thus, no communication will be possible
27 the condition of SCL being unresponsive and report an error to the upper
62 being pulled low by the device while SCL is high. So, similar to the "sda" file
65 SDA after toggling SCL.
81 register 0x00 (if it has registers) when further clock pulses happen on SCL.
99 Arbitration lost is achieved by waiting for SCL going down by the master under
104 should be detected beforehand. Also note, that SCL going down is monitored
129 Start of a transfer is detected by waiting for SCL going down by the master
/Documentation/devicetree/bindings/i3c/
Di3c.yaml42 i3c-scl-hz:
44 Frequency of the SCL signal used for I3C transfers. When undefined, the
49 i2c-scl-hz:
51 Frequency of the SCL signal used for I2C transfers. When undefined, the
99 supports high frequency on SCL
167 i2c-scl-hz = <100000>;
Dcdns,i3c-master.yaml52 i2c-scl-hz = <100000>;
/Documentation/devicetree/bindings/iio/temperature/
Dti,tmp007.yaml28 0 SCL 0x43
32 1 SCL 0x47
Dmelexis,mlx90614.yaml30 driving the SCL line. If no GPIO is given, power management is disabled.
/Documentation/devicetree/bindings/pinctrl/
Dcirrus,lochnagar.yaml107 dsp-dmicdat1, dsp-dmicclk2, dsp-dmicdat2, i2c2-scl,
108 i2c2-sda, i2c3-scl, i2c3-sda, i2c4-scl, i2c4-sda,
136 i2c2-scl, i2c2-sda, i2c3-scl, i2c3-sda, i2c4-scl,
/Documentation/i2c/muxes/
Di2c-mux-gpio.rst16 | | SCL/SDA | |-------------- | |
25 SCL/SDA of the master I2C bus is multiplexed to bus segment 1..M
/Documentation/devicetree/bindings/display/panel/
Draspberrypi,7inch-touchscreen.yaml56 scl-gpios = <&gpio 28 0>;
/Documentation/dev-tools/
Dgpio-sloppy-logic-analyzer.rst50 probe-names = "SCL", "SDA";
75 edge on SDA while SCL stays high, i.e. ``-t 1H+2F``. Last is the duration, let
/Documentation/i2c/busses/
Di2c-parport.rst57 SCL ----------x--------o |-----------x------------------- pin 2
97 - Obviously you cannot read SCL (so it's not really standard-compliant).
112 SCL ----------x--------x--| o---x------------------------ pin 15
Di2c-mlxcpld.rst35 Configure the width of I2C SCL half clock cycle (in 4 LPC_CLK
/Documentation/hwmon/
Dmax127.rst27 communication among multiple devices using SDA and SCL lines.
/Documentation/gpu/amdgpu/display/
Ddc-glossary.rst212 SCL
/Documentation/driver-api/
Di2c.rst8 the same bus. I2C only needs two signals (SCL for clock, SDA for data),
/Documentation/devicetree/bindings/hwmon/
Dadi,max31827.yaml59 Enables timeout. Bus timeout resets the I2C-compatible interface when SCL

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