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/Documentation/devicetree/bindings/mmc/
Dsocionext,uniphier-sd.yaml4 $id: http://devicetree.org/schemas/mmc/socionext,uniphier-sd.yaml#
7 title: UniPhier SD/SDIO/eMMC controller
16 - socionext,uniphier-sd-v2.91
17 - socionext,uniphier-sd-v3.1
18 - socionext,uniphier-sd-v3.1.1
63 - description: ID of SD instance
66 The argument is the ID of SD instance.
75 const: socionext,uniphier-sd-v2.91
100 sd: mmc@5a400000 {
101 compatible = "socionext,uniphier-sd-v2.91";
[all …]
Daspeed,sdhci.yaml8 title: ASPEED SD/SDIO/MMC Controller
15 The ASPEED SD/SDIO/eMMC controller exposes two slots implementing the SDIO
26 - aspeed,ast2400-sd-controller
27 - aspeed,ast2500-sd-controller
28 - aspeed,ast2600-sd-controller
39 description: The SD/SDIO controller clock gate
58 description: The SD bus clock
61 description: The SD interrupt shared between both slots
85 compatible = "aspeed,ast2500-sd-controller";
Dcdns,sdhci.yaml7 title: Cadence SD/SDIO/eMMC Host Controller (SD4HC)
39 cdns,phy-input-delay-sd-highspeed:
40 description: Value of the delay in the input path for SD high-speed timing
51 cdns,phy-input-delay-sd-uhs-sdr12:
52 description: Value of the delay in the input path for SD UHS SDR12 timing
57 cdns,phy-input-delay-sd-uhs-sdr25:
58 description: Value of the delay in the input path for SD UHS SDR25 timing
63 cdns,phy-input-delay-sd-uhs-sdr50:
64 description: Value of the delay in the input path for SD UHS SDR50 timing
69 cdns,phy-input-delay-sd-uhs-ddr50:
[all …]
Dsdhci-st.txt1 * STMicroelectronics sdhci-st MMC/SD controller
22 - pinctrl-0: Phandle referencing pin configuration of the sd/emmc controller.
49 supply in eMMC/SD specs.
51 - sd-uhs-sdr50: To enable the SDR50 in the mmcss.
54 - sd-uhs-sdr104: To enable the SDR104 in the mmcss.
57 - sd-uhs-ddr50: To enable the DDR50 in the mmcss.
75 /* Example SD stih407 family configuration */
107 sd-uhs-sdr50;
108 sd-uhs-sdr104;
109 sd-uhs-ddr50;
Dmmc-controller.yaml52 # *NOTE* on CD and WP polarity. To use common for all SD/MMC host
94 - for SD/SDIO cards the SDR104 mode has a max supported
130 cap-sd-highspeed:
133 SD high-speed timing is supported.
140 sd-uhs-sdr12:
143 SD UHS SDR12 speed is supported.
145 sd-uhs-sdr25:
148 SD UHS SDR25 speed is supported.
150 sd-uhs-sdr50:
153 SD UHS SDR50 speed is supported.
[all …]
Dsdhci-am654.yaml62 description: Output tap delay for SD/MMC legacy timing
73 ti,otap-del-sel-sd-hs:
74 description: Output tap delay for SD high speed timing
80 description: Output tap delay for SD UHS SDR12 timing
86 description: Output tap delay for SD UHS SDR25 timing
92 description: Output tap delay for SD UHS SDR50 timing
98 description: Output tap delay for SD UHS SDR104 timing
104 description: Output tap delay for SD UHS DDR50 timing
132 description: Input tap delay for SD/MMC legacy timing
143 ti,itap-del-sel-sd-hs:
[all …]
Dk3-dw-mshc.txt7 a SoC with storage medium such as eMMC or SD/MMC cards. This file documents
49 cap-sd-highspeed;
58 cap-sd-highspeed;
59 sd-uhs-sdr12;
60 sd-uhs-sdr25;
Dmarvell,xenon-sdhci.yaml84 All those types of PHYs can support eMMC, SD and SDIO. Please note that
128 always occur with PHY enabled in eMMC HS SDR, SD SDR12, SD SDR25,
129 SD Default Speed and HS mode and eMMC legacy speed mode.
157 - sd
161 If "sd" is selected, SoC PHY PAD is set as 3.3V at the beginning
215 no-sd;
222 // For SD/SDIO
254 no-sd;
263 // For SD/SDIO with compatible "marvell,armada-3700-sdhci":
278 marvell,pad-type = "sd";
Dcavium-mmc.txt4 for MMC and SD types of memory cards.
7 as the speed of SD standard 4.0. Only 3.3 Volt is supported.
45 cap-sd-highspeed;
/Documentation/misc-devices/
Dxilinx_sdfec.rst4 Xilinx SD-FEC Driver
10 This driver supports SD-FEC Integrated Block for Zynq |Ultrascale+ (TM)| RFSoCs.
15 For a full description of SD-FEC core features, see the `SD-FEC Product Guide (PG256) <https://www.…
24 Missing features, known issues, and limitations of the SD-FEC driver are as
28 - Reset of the SD-FEC Integrated Block is not controlled by this driver
32 `linux-xlnx/Documentation/devicetree/bindings/misc/xlnx,sd-fec.yaml <https://github.com/Xilinx/linu…
38 The driver works with the SD-FEC core in two modes of operation:
50 - Activate the SD-FEC core
51 - Monitor the SD-FEC core for errors
52 - Retrieve the status and configuration of the SD-FEC core
[all …]
/Documentation/devicetree/bindings/iio/adc/
Dsigma-delta-modulator.yaml15 "sd-modulator" can be used as a generic SD modulator,
18 - sd-modulator
44 // Backend binding example. SD modulator configured as an IIO backend device
46 compatible = "sd-modulator";
52 // Legacy binding example. SD modulator configured as an IIO channel provider
54 compatible = "sd-modulator";
/Documentation/driver-api/mmc/
Dmmc-dev-attrs.rst2 SD and MMC Block Device Attributes
6 SD or MMC device.
14 SD and MMC Device Attributes
22 scr SD Card Configuration Register (SD only)
25 (SD and MMCv1 only)
27 (SD and MMCv1 only)
32 (SD and MMCv4 only)
51 always one 512 byte sector. For SD, "erase_size" is 512
54 SD/MMC cards can erase an arbitrarily large area up to and
72 (especially for SD where it is just one sector),
[all …]
/Documentation/devicetree/bindings/reset/
Dsocionext,uniphier-reset.yaml27 - description: Media I/O (MIO) reset, SD reset
32 - socionext,uniphier-pro5-sd-reset
33 - socionext,uniphier-pxs2-sd-reset
35 - socionext,uniphier-ld11-sd-reset
36 - socionext,uniphier-ld20-sd-reset
37 - socionext,uniphier-pxs3-sd-reset
38 - socionext,uniphier-nx1-sd-reset
/Documentation/devicetree/bindings/clock/
Dsocionext,uniphier-clock.yaml27 - description: Media I/O (MIO) clock, SD clock
32 - socionext,uniphier-pro5-sd-clock
33 - socionext,uniphier-pxs2-sd-clock
35 - socionext,uniphier-ld20-sd-clock
36 - socionext,uniphier-pxs3-sd-clock
37 - socionext,uniphier-nx1-sd-clock
Didt,versaclock5.yaml38 SH SP Output when the SD/OE pin is Low/High
88 shut down if the SD/OE pin is driven high. If 0, this disables the
90 the value of the SD/OE pin. This property corresponds to the SH
97 If 1, this enables output when the SD/OE pin is high, and disables
98 output when the SD/OE pin is low. If 0, this disables output when
99 the SD/OE pin is high, and enables output when the SD/OE pin is
179 /* Set the SD/OE pin's settings */
/Documentation/devicetree/bindings/soc/socionext/
Dsocionext,uniphier-sdctrl.yaml7 title: Socionext UniPhier SD interface logic
13 SD interface logic implemented on Socionext UniPhier SoCs is
14 attached outside SDHC, and has some SD related functions such as
53 compatible = "socionext,uniphier-ld20-sd-clock";
58 compatible = "socionext,uniphier-ld20-sd-reset";
Dsocionext,uniphier-mioctrl.yaml15 SD/eMMC, and MIO-DMAC.
18 Recent SoCs have SD interface logic specialized only for SD functions
/Documentation/devicetree/bindings/arm/
Dqcom-soc.yaml26 pattern: "^qcom,.*(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1e)[0-9]+.*$"
34 - pattern: "^qcom,(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1e)[0-9]+(pro)?-.*$"
39 - pattern: "^qcom,[ak]pss-wdt-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm)[0-9]+.*$"
40 - pattern: "^qcom,gcc-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm)[0-9]+.*$"
41 - pattern: "^qcom,mmcc-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm)[0-9]+.*$"
42 - pattern: "^qcom,pcie-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1e)[0-9]+.*$"
43 - pattern: "^qcom,rpm-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm)[0-9]+.*$"
44 - pattern: "^qcom,scm-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1e)[0-9]+.*$"
/Documentation/devicetree/bindings/media/i2c/
Dadv7343.txt6 definition (SD), enhanced definition (ED), or high definition (HD) video
22 - ad,adv7343-sd-config-dac-out: array configure SD DAC Output's 1 and 2, 0 = OFF
42 /* Use SD DAC output 1 */
43 adi,sd-dac-enable = <1 0>;
/Documentation/devicetree/bindings/dma/
Dstericsson,dma40.yaml23 1: SD/MMC controller 0 (unused)
24 2: SD/MMC controller 1 (unused)
25 3: SD/MMC controller 2 (unused)
50 28: SD/MMC controller 2
51 29: SD/MMC controller 0
54 32: SD/MMC controller 1
63 41: SD/MMC controller 3
64 42: SD/MMC controller 4
65 43: SD/MMC controller 5
/Documentation/translations/zh_CN/video4linux/
Dv4l2-framework.txt250 int (*log_status)(struct v4l2_subdev *sd);
251 int (*init)(struct v4l2_subdev *sd, u32 val);
287 v4l2_subdev_init(sd, &ops);
298 err = media_entity_pads_init(&sd->entity, npads, pads);
307 media_entity_cleanup(&sd->entity);
323 int err = v4l2_device_register_subdev(v4l2_dev, sd);
333 v4l2_device_unregister_subdev(sd);
335 此后，子设备模块就可卸载，且 sd->dev == NULL。
339 err = sd->ops->core->g_std(sd, &norm);
343 err = v4l2_subdev_call(sd, core, g_std, &norm);
[all …]
/Documentation/driver-api/media/
Dv4l2-subdev.rst54 int (*log_status)(struct v4l2_subdev *sd);
55 int (*init)(struct v4l2_subdev *sd, u32 val);
93 (:c:type:`sd <v4l2_subdev>`, &\ :c:type:`ops <v4l2_subdev_ops>`).
96 Afterwards you need to initialize :c:type:`sd <v4l2_subdev>`->name with a
110 err = media_entity_pads_init(&sd->entity, npads, pads);
123 media_entity_cleanup(&sd->entity);
167 (:c:type:`v4l2_dev <v4l2_device>`, :c:type:`sd <v4l2_subdev>`).
179 (:c:type:`sd <v4l2_subdev>`).
182 :c:type:`sd <v4l2_subdev>`->dev == ``NULL``.
303 err = sd->ops->core->g_std(sd, &norm);
[all …]
/Documentation/devicetree/bindings/misc/
Dxlnx,sd-fec.yaml4 $id: http://devicetree.org/schemas/misc/xlnx,sd-fec.yaml#
23 const: xlnx,sd-fec-1.1
66 The SD-FEC integrated block supports Low Density Parity Check (LDPC)
125 sd-fec@a0040000 {
126 compatible = "xlnx,sd-fec-1.1";
/Documentation/devicetree/bindings/pinctrl/
Dmarvell,armada-375-pinctrl.txt40 mpp24 24 gpio, led(p0), ge1(rxd0), sd(cmd), uart0(rts)
41 mpp25 25 gpio, led(p2), ge1(rxd1), sd(d0), uart0(cts)
42 mpp26 26 gpio, pcie0(clkreq), ge1(rxd2), sd(d2), uart1(rts)
43 mpp27 27 gpio, pcie1(clkreq), ge1(rxd3), sd(d1), uart1(cts)
44 mpp28 28 gpio, led(p3), ge1(txctl), sd(clk)
45 mpp29 29 gpio, pcie1(clkreq), ge1(rxclk), sd(d3)
/Documentation/devicetree/bindings/regulator/
Dvqmmc-ipq4019-regulator.yaml7 title: Qualcomm IPQ4019 VQMMC SD LDO regulator
13 Qualcomm IPQ4019 SoC-s feature a built a build SD/EMMC controller,

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