Searched full:sdmmc (Results 1 – 11 of 11) sorted by relevance
| /Documentation/devicetree/bindings/mmc/ |
| D | nvidia,tegra20-sdhci.yaml | 228 - const: sdmmc-3v3
230 - const: sdmmc-1v8
232 - const: sdmmc-3v3-drv
234 - const: sdmmc-1v8-drv
237 - const: sdmmc-3v3-drv
239 - const: sdmmc-1v8-drv
242 - const: sdmmc-1v8-drv
257 - const: sdmmc-3v3
259 - const: sdmmc-1v8
296 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8",
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| D | synopsys-dw-mshc.yaml | 46 - description: register offset that controls the SDMMC clock phase
50 that contains the SDMMC clock-phase control register. The first value is
52 SDMMC clock phase register, and the 3rd value is the bit shift for the
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| D | vt8500-sdmmc.txt | 4 by mmc.txt and the properties used by the wmt-sdmmc driver.
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| D | atmel,sama5d2-sdhci.yaml | 54 capacitor (see "SDMMC I/O Calibration" chapter).
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| D | rockchip-dw-mshc.yaml | 114 sdmmc: mmc@ff0c0000 {
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| /Documentation/devicetree/bindings/edac/ |
| D | socfpga-eccmgr.txt | 125 SDMMC FIFO ECC
127 - compatible : Should be "altr,socfpga-sdmmc-ecc"
224 sdmmc-ecc@ff8c2c00 {
225 compatible = "altr,socfpga-sdmmc-ecc";
296 SDMMC FIFO ECC
298 - compatible : Should be "altr,socfpga-s10-sdmmc-ecc"
376 sdmmc-ecc@ff8c8c00 {
377 compatible = "altr,socfpga-s10-sdmmc-ecc";
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| /Documentation/devicetree/bindings/clock/ |
| D | altr_socfpga.txt | 27 the SDMMC CIU clock. The first value is the clk_sample(smpsel), and the second
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| D | st,stm32mp25-rcc.yaml | 44 - description: CK_SCMI_ICN_SDMMC SDMMC interconnect bus clock
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| D | samsung,exynos5433-clock.yaml | 39 # CMU_FSYS which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs
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| /Documentation/devicetree/bindings/arm/tegra/ |
| D | nvidia,tegra186-pmc.yaml | 213 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
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| /Documentation/devicetree/bindings/power/ |
| D | rockchip-io-domain.yaml | 298 sdmmc-supply:
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