Searched full:sdram (Results 1 – 25 of 45) sorted by relevance
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| /Documentation/devicetree/bindings/arm/altera/ |
| D | socfpga-sdram-edac.txt | 1 Altera SOCFPGA SDRAM Error Detection & Correction [EDAC]
2 The EDAC accesses a range of registers in the SDRAM controller.
5 - compatible : should contain "altr,sdram-edac" or "altr,sdram-edac-a10"
7 - interrupts : Should contain the SDRAM ECC IRQ in the
12 compatible = "altr,sdram-edac";
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| /Documentation/devicetree/bindings/edac/ |
| D | aspeed-sdram-edac.txt | 15 - "aspeed,ast2400-sdram-edac"
16 - "aspeed,ast2500-sdram-edac"
17 - "aspeed,ast2600-sdram-edac"
18 - reg: sdram controller register set should be <0x1e6e0000 0x174>
24 edac: sdram@1e6e0000 {
25 compatible = "aspeed,ast2500-sdram-edac";
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| /Documentation/devicetree/bindings/memory-controllers/ |
| D | marvell,mvebu-sdram-controller.yaml | 4 $id: http://devicetree.org/schemas/memory-controllers/marvell,mvebu-sdram-controller.yaml#
7 title: Marvell MVEBU SDRAM controller
15 const: marvell,armada-xp-sdram-controller
29 compatible = "marvell,armada-xp-sdram-controller";
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| D | samsung,s5pv210-dmc.yaml | 13 Dynamic Memory Controller interfaces external JEDEC DDR-type SDRAM.
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| D | mediatek,mt7621-memc.yaml | 7 title: MT7621 SDRAM controller
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | ralink,rt2880-pinctrl.yaml | 38 enum: [gpio, i2c, spi, uartlite, jtag, mdio, sdram, pci]
57 enum: [i2c, spi, uartlite, jtag, mdio, sdram, pci]
107 const: sdram
111 enum: [sdram]
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| D | ralink,rt305x-pinctrl.yaml | 39 pcm gpio, pcm i2s, pcm uartf, rgmii, sdram, spi, uartf,
59 enum: [i2c, jtag, mdio, rgmii, sdram, spi, uartf, uartlite]
154 const: sdram
158 enum: [sdram]
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| /Documentation/devicetree/bindings/arm/omap/ |
| D | dmm.txt | 4 SDRAM controllers (called EMIFs on OMAP). DMM manages various aspects of memory
5 accesses such as priority generation amongst initiators, configuration of SDRAM
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| /Documentation/driver-api/memory-devices/ |
| D | ti-emif.rst | 4 TI EMIF SDRAM Controller Driver
29 SoCs. EMIF is an SDRAM controller that, based on its revision,
30 supports one or more of DDR2, DDR3, and LPDDR2 SDRAM protocols.
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| /Documentation/devicetree/bindings/memory-controllers/ti/ |
| D | emif.txt | 1 * EMIF family of TI SDRAM controllers
3 EMIF - External Memory Interface - is an SDRAM controller used in
57 has capability for generating SDRAM temperature alerts
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| /Documentation/devicetree/bindings/memory-controllers/ddr/ |
| D | jedec,lpddr-props.yaml | 48 Density in megabits of SDRAM chip. Decoded from Mode Register 8.
68 IO bus width in bits of SDRAM chip. Decoded from Mode Register 8.
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| D | jedec,lpddr2.yaml | 7 title: LPDDR2 SDRAM compliant to JEDEC JESD209-2
37 Revision 1 value of SDRAM chip. Obtained from device datasheet.
45 Revision 2 value of SDRAM chip. Obtained from device datasheet.
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| D | jedec,lpddr4.yaml | 7 title: LPDDR4 SDRAM compliant to JEDEC JESD209-4
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| D | jedec,lpddr5.yaml | 7 title: LPDDR5 SDRAM compliant to JEDEC JESD209-5
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| /Documentation/devicetree/bindings/fpga/ |
| D | altr,socfpga-fpga2sdram-bridge.yaml | 7 title: Altera FPGA To SDRAM Bridge
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| /Documentation/arch/arm/stm32/ |
| D | stm32mp13-overview.rst | 19 - FMC controller to connect SDRAM, NOR and NAND memories
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| D | stm32mp151-overview.rst | 19 - FMC controller to connect SDRAM, NOR and NAND memories
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| D | stm32f429-overview.rst | 13 - External memory support through FMC controller (PSRAM, SDRAM, NOR, NAND)
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| D | stm32h743-overview.rst | 13 - FMC controller to connect SDRAM, NOR and NAND memories
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| D | stm32h750-overview.rst | 13 - FMC controller to connect SDRAM, NOR and NAND memories
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| D | stm32f746-overview.rst | 13 - FMC controller to connect SDRAM, NOR and NAND memories
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| D | stm32f769-overview.rst | 13 - FMC controller to connect SDRAM, NOR and NAND memories
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| /Documentation/devicetree/bindings/clock/ |
| D | mvebu-core-clock.txt | 30 3 = hclk (SDRAM Controller Internal Clock)
31 4 = dclk (SDRAM Interface Clock)
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| /Documentation/fb/ |
| D | matroxfb.rst | 169 - 4 -> 2x512Kx16 chips, 8/16MB onboard, probably sdram only
174 - 0 -> 2x512Kx16 SDRAM, 16/32MB
178 - 3 -> 4x512Kx32 SDRAM, 32MB
180 - 5 -> 2x1Mx32 SDRAM, 32MB
184 You should use sdram or sgram parameter in addition to memtype
195 sdram tells to driver that you have Gxx0 with SDRAM memory.
319 - Gxx0 SGRAM/SDRAM is not autodetected.
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| /Documentation/devicetree/bindings/reserved-memory/ |
| D | nvidia,tegra264-bpmp-shmem.yaml | 27 description: The physical address and size of the shared SDRAM region
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