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/Documentation/devicetree/bindings/nvmem/
Dfsl,layerscape-sfp.yaml4 $id: http://devicetree.org/schemas/nvmem/fsl,layerscape-sfp.yaml#
13 SFP is the security fuse processor which among other things provides a
23 - description: Trust architecture 2.1 SFP
25 - const: fsl,ls1021a-sfp
26 - description: Trust architecture 3.0 SFP
28 - const: fsl,ls1028a-sfp
36 The SFP clock. Typically, this is the platform clock divided by 4.
39 const: sfp
41 ta-prog-sfp-supply:
58 compatible = "fsl,ls1028a-sfp";
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Dfsl,t1023-sfp.yaml4 $id: http://devicetree.org/schemas/nvmem/fsl,t1023-sfp.yaml#
13 Read support for the eFuses (SFP) on NXP QorIQ series SoC's.
20 const: fsl,t1023-sfp
34 compatible = "fsl,t1023-sfp";
/Documentation/devicetree/bindings/net/
Dsff,sfp.yaml4 $id: http://devicetree.org/schemas/net/sff,sfp.yaml#
7 title: Small Form Factor (SFF) Committee Small Form-factor Pluggable (SFP)
16 - sff,sfp # for SFP modules
22 phandle of an I2C bus controller for the SFP two wire serial
68 output gpio signal (SFP+ only), low - low Tx rate, high - high Tx rate. Must
90 - | # Direct serdes to SFP connection
93 sfp1: sfp {
94 compatible = "sff,sfp";
108 sfp = <&sfp1>;
111 - | # Serdes to PHY to SFP connection
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Dmicrochip,lan966x-switch.yaml96 the PHY or SFP.
108 sfp:
110 Phandle of an SFP.
123 - sfp
163 sfp = <&sfp_eth1>;
Dmicrochip,sparx5-switch.yaml124 - sfp
168 sfp = <&sfp_eth60>;
177 sfp = <&sfp_eth61>;
186 sfp = <&sfp_eth62>;
195 sfp = <&sfp_eth63>;
Dethernet-controller.yaml144 sfp:
147 Specifies a reference to a node representing a SFP cage.
Dethernet-phy.yaml197 sfp:
200 Specifies a reference to a node representing a SFP cage.
Dapm-xgene-enet.txt50 - rxlos-gpios: Input gpio from SFP+ module to indicate availability of
Daltr,tse.yaml133 sfp = <&sfp0>;
Dqcom,qca807x.yaml53 the presence of a connected SFP device.
Dmarvell,pp2.yaml300 sfp = <&sfp_eth3>;
/Documentation/networking/
Dphy-link-topology.rst29 for example, using SFP transceivers (although that's not the only specific case).
32 interface, that can directly be fed to an SFP cage, such as SGMII, 1000BaseX,
35 The link topology then looks like this (when an SFP module is inserted) ::
38 | MAC | ------- | SFP Module |
44 | MAC | -------- | PHY (on SFP) |
47 In this case, the SFP PHY is handled by phylib, and registered by phylink through
48 its SFP upstream ops.
51 we can't directly connect them to an SFP cage. However, some PHYs can be used
53 serialized MII interface fed to the SFP ::
56 | MAC | ------- | PHY (media converter) | ------- | PHY (on SFP) |
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Dkapi.rst141 and SFF modules (eg, hot-pluggable SFP) that may contain PHYs. PHYLINK
149 SFP support
152 .. kernel-doc:: drivers/net/phy/sfp-bus.c
155 .. kernel-doc:: include/linux/sfp.h
158 .. kernel-doc:: drivers/net/phy/sfp-bus.c
Dsfp-phylink.rst15 and SFP (Small Formfactor Pluggable) modules at present.
69 Rough guide to converting a network driver to sfp/phylink
73 phylib to the sfp/phylink support. Please send patches to improve
170 fixed link properties, and will also contain the sfp property.
403 For information describing the SFP cage in DT, please see the binding
405 ``Documentation/devicetree/bindings/net/sff,sfp.yaml``.
Dindex.rst31 sfp-phylink
Dethtool-netlink.rst225 ``ETHTOOL_MSG_MODULE_EEPROM_GET`` read SFP module EEPROM
275 ``ETHTOOL_MSG_MODULE_EEPROM_GET_REPLY`` read SFP module EEPROM
1486 select the FEC mode automatically based on the parameters of the SFP module.
1531 ``ETHTOOL_A_FEC_AUTO`` requests the driver to choose FEC mode based on SFP
2234 its parent PHY through an SFP
2235 bus, the name of this sfp bus
2236 ``ETHTOOL_A_PHY_DOWNSTREAM_SFP_NAME`` string if the phy controls an sfp bus,
2237 the name of the sfp bus
Dphy.rst289 compliance board plugged into the host XFP/SFP connector. Therefore,
/Documentation/networking/device_drivers/ethernet/intel/
Dixgbe.rst35 SFP+ Devices with Pluggable Optics
44 - When 82599-based SFP+ devices are connected back to back, they should be set
53 | Intel | DUAL RATE 1G/10G SFP+ SR (bailed) | FTLX8571D3BCV-IT |
55 | Intel | DUAL RATE 1G/10G SFP+ SR (bailed) | AFBR-703SDZ-IN2 |
57 | Intel | DUAL RATE 1G/10G SFP+ SR (bailed) | AFBR-703SDDZ-IN1 |
61 | Intel | DUAL RATE 1G/10G SFP+ LR (bailed) | FTLX1471D3BCV-IT |
63 | Intel | DUAL RATE 1G/10G SFP+ LR (bailed) | AFCT-701SDZ-IN2 |
65 | Intel | DUAL RATE 1G/10G SFP+ LR (bailed) | AFCT-701SDDZ-IN1 |
68 The following is a list of 3rd party SFP+ modules that have received some
74 | Finisar | SFP+ SR bailed, 10g single rate | FTLX8571D3BCL |
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Di40e.rst46 SFP+ and QSFP+ Devices
131 balancing (in SFP mode only).
/Documentation/devicetree/bindings/arm/
Dmicrochip,sparx5.yaml35 gigabit switch with 20 SFP ports. It features spi-nor and
/Documentation/devicetree/bindings/phy/
Dmediatek,mt7988-xfi-tphy.yaml46 the SFP specification.
/Documentation/devicetree/bindings/pinctrl/
Dmicrochip,sparx5-sgpio.yaml16 connect control signals from SFP modules and to act as an LED
/Documentation/netlink/specs/
Dethtool.yaml1135 name: upstream-sfp-name
1138 name: downstream-sfp-name
1956 - upstream-sfp-name
1957 - downstream-sfp-name
/Documentation/networking/device_drivers/ethernet/aquantia/
Datlantic.rst27 SFP+ Devices (for AQC-100 based adapters)
30 This release tested with passive Direct Attach Cables (DAC) and SFP+/LC
/Documentation/devicetree/bindings/net/dsa/
Dmediatek,mt7530.yaml66 to gmac1 of the SoC for this to work. Ubiquiti EdgeRouter X SFP is wired