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/Documentation/devicetree/bindings/reset/
Dzynq-reset.txt9 - reg: SLCR offset and size taken via syscon <0x200 0x48>
10 - syscon: <&slcr>
11 This should be a phandle to the Zynq's SLCR registers.
14 The Zynq Reset Manager needs to be a childnode of the SLCR.
21 syscon = <&slcr>;
/Documentation/devicetree/bindings/fpga/
Dxilinx-zynq-fpga-mgr.yaml32 Phandle to syscon block which provide access to SLCR registers
51 syscon = <&slcr>;
/Documentation/devicetree/bindings/pinctrl/
Dxlnx,pinctrl-zynq.yaml34 description: Specifies the base address and size of the SLCR space.
39 phandle to the SLCR.
186 syscon = <&slcr>;
/Documentation/devicetree/bindings/clock/
Dzynq-7000.txt17 - reg : SLCR offset and size taken via syscon < 0x100 0x100 >