Searched full:sme (Results 1 – 10 of 10) sorted by relevance
| /Documentation/arch/x86/ |
| D | amd-memory-encryption.rst | 7 Secure Memory Encryption (SME) and Secure Encrypted Virtualization (SEV) are
10 SME provides the ability to mark individual pages of memory as encrypted using
13 DRAM. SME can therefore be used to protect the contents of DRAM from physical
20 memory may be encrypted with hypervisor key. When SME is enabled, the hypervisor
21 key is the same key which is used in SME.
42 Support for SME and SEV can be determined through the CPUID instruction. The
43 CPUID function 0x8000001f reports information related to SME::
46 Bit[0] indicates support for SME
56 If support for SME is present, MSR 0xc00100010 (MSR_AMD64_SYSCFG) can be used to
57 determine if SME is enabled and/or to enable memory encryption::
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| /Documentation/arch/arm64/ |
| D | sme.rst | 6 order to support use of the ARM Scalable Matrix Extension (SME).
11 included in SME.
13 This document does not aim to describe the SME architecture or programmer's
15 model features for SME is included in Appendix A.
24 * The presence of SME is reported to userspace via HWCAP2_SME in the aux vector
25 AT_HWCAP2 entry. Presence of this flag implies the presence of the SME
27 described in this document. SME is reported in /proc/cpuinfo as "sme".
34 * Support for the execution of SME instructions in userspace can also be
36 instruction, and checking that the value of the SME field is nonzero. [3]
42 * There are a number of optional SME features, presence of these is reported
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| D | index.rst | 27 sme
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| D | sve.rst | 12 (SME).
63 * On hardware that supports the SME extensions, HWCAP2_SME will also be
64 reported in the AT_HWCAP2 aux vector entry. Among other things SME adds
66 separate SME vector length and the same Z/V registers. See sme.rst
72 ptrace(PTRACE_GETREGSET, pid, NT_ARM_SVE, &iov). Note that when SME is
362 payload is available, this is only possible when SME is implemented.
380 * In systems supporting SME when in streaming mode a GETREGSET for
396 * Where SME is implemented it is not possible to GETREGSET the register
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| D | elf_hwcaps.rst | 255 Functionality implied by ID_AA64PFR1_EL1.SME == 0b0001, as described
256 by Documentation/arch/arm64/sme.rst.
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| D | cpu-feature-registers.rst | 180 | SME | [27-24] | y |
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| /Documentation/admin-guide/kdump/ |
| D | vmcoreinfo.rst | 389 AMD-specific with SME support: it indicates the secure memory encryption
391 encrypted. If SME is enabled in the first kernel, the crash kernel's
393 mask. This is used to remove the SME mask and obtain the true physical
397 additional SME-relevant info can be placed in that variable.
401 [ misc ][ enc bit ][ other misc SME info ]
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| /Documentation/devicetree/bindings/net/ |
| D | microchip,sparx5-switch.yaml | 29 equipment in SMB, SME, and Enterprise where high port count
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| /Documentation/virt/hyperv/ |
| D | coco.rst | 25 * AMD processor with SEV-SNP. Hyper-V does not run guest VMs with AMD SME,
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| /Documentation/admin-guide/ |
| D | kernel-parameters.txt | 3500 mem_encrypt= [X86-64] AMD Secure Memory Encryption (SME) control
3503 mem_encrypt=on: Activate SME
3504 mem_encrypt=off: Do not activate SME
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