Searched full:smp (Results 1 – 25 of 130) sorted by relevance
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| /Documentation/devicetree/bindings/sram/ |
| D | sram.yaml | 81 - allwinner,sun9i-a80-smp-sram
85 - amlogic,meson8-smp-sram
86 - amlogic,meson8b-smp-sram
92 - renesas,smp-sram
93 - rockchip,rk3066-smp-sram
96 - socionext,milbeaut-smp-sram
171 smp-sram@100 {
187 // Samsung SMP-capable Exynos SoCs use part of the SYSRAM for the bringup
201 smp-sram@0 {
206 smp-sram@53000 {
[all …]
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| /Documentation/devicetree/bindings/arm/ |
| D | cpus.yaml | 219 - actions,s500-smp
222 - allwinner,sun9i-a80-smp
223 - allwinner,sun8i-a83t-smp
224 - amlogic,meson8-smp
225 - amlogic,meson8b-smp
226 - arm,realview-smp
227 - aspeed,ast2600-smp
230 - brcm,bcm2836-smp
232 - brcm,bcm-nsp-smp
234 - marvell,armada-375-smp
[all …]
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| /Documentation/devicetree/bindings/arm/cpu-enable-method/ |
| D | marvell,berlin-smp | 2 Secondary CPU enable-method "marvell,berlin-smp" binding
5 This document describes the "marvell,berlin-smp" method for enabling secondary
6 CPUs. To apply to all CPUs, a single "marvell,berlin-smp" enable method should
9 Enable method name: "marvell,berlin-smp"
23 enable-method = "marvell,berlin-smp";
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| D | al,alpine-smp | 2 Secondary CPU enable-method "al,alpine-smp" binding
5 This document describes the "al,alpine-smp" method for
7 "al,alpine-smp" enable method should be defined in the
10 Enable method name: "al,alpine-smp"
35 enable-method = "al,alpine-smp";
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| D | nuvoton,npcm750-smp | 2 Secondary CPU enable-method "nuvoton,npcm750-smp" binding
5 To apply to all CPUs, a single "nuvoton,npcm750-smp" enable method should be
8 Enable method name: "nuvoton,npcm750-smp"
22 enable-method = "nuvoton,npcm750-smp";
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | csky,mpintc.txt | 6 SMP soc, and it also could be used in non-SMP system.
23 Description: Describes SMP interrupt controller
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| D | brcm,bcm6345-l1-intc.txt | 35 If multiple reg ranges and interrupt-parent entries are present on an SMP
36 system, the driver will allow IRQ SMP affinity to be set up through the
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| D | brcm,bcm7038-l1-intc.yaml | 30 If multiple reg ranges and interrupt-parent entries are present on an SMP
31 system, the driver will allow IRQ SMP affinity to be set up through the
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| D | jcore,aic.txt | 9 - reg: Memory region(s) for configuration. For SMP, there should be one
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| /Documentation/devicetree/bindings/clock/ |
| D | stericsson,u8500-clks.yaml | 17 clocks - RTC (32 kHz), CPU clock (SMP TWD), PRCMU (power reset and
101 smp-twd-clock:
102 description: A subnode for the ARM SMP Timer Watchdog cluster with zero
138 - smp-twd-clock
171 smp_twd_clk: smp-twd-clock {
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| /Documentation/arch/x86/i386/ |
| D | IO-APIC.rst | 9 Most (all) Intel-MP compliant SMP boards have the so-called 'IO-APIC',
15 Linux supports all variants of compliant SMP boards, including ones with
20 usually worked around by the kernel. If your MP-compliant SMP board does
21 not boot Linux, then consult the linux-smp mailing list archives first.
120 Good luck and mail to linux-smp@vger.kernel.org or
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| /Documentation/devicetree/bindings/arm/omap/ |
| D | mpu.txt | 25 - For an OMAP5 SMP system:
32 - For an OMAP4 SMP system:
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| /Documentation/devicetree/bindings/timer/ |
| D | csky,mptimer.txt | 5 C-SKY multi-processors timer is designed for C-SKY SMP system and the
17 Description: Describes SMP timer
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| D | snps,archs-gfrc.txt | 2 - clocksource provider for SMP SoC
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| D | jcore,pit.txt | 7 - reg: Memory region(s) for timer/clocksource registers. For SMP,
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| /Documentation/devicetree/bindings/csky/ |
| D | cpus.txt | 9 Only SMP system need to care about the cpus node and single processor
35 Description: Describes one of SMP cores
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| /Documentation/scsi/ |
| D | libsas.rst | 421 implements an SMP portal (Note: this is *NOT* an SMP port),
422 to which user space applications can send SMP requests and
423 receive SMP responses.
427 1. Build the SMP frame you want to send. The format and layout
432 2. Open the expander's SMP portal sysfs file in RW mode.
453 argument, the sysfs file name of the SMP portal to the
457 The SMP portal gives you complete control of the expander,
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| /Documentation/core-api/irq/ |
| D | irq-affinity.rst | 2 SMP IRQ affinity
22 it to CPU4-7 (this is an 8-CPU SMP box)::
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| /Documentation/devicetree/bindings/cpufreq/ |
| D | cpufreq-spear.txt | 5 It supports both uniprocessor (UP) and symmetric multiprocessor (SMP) systems
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| /Documentation/devicetree/bindings/arm/hisilicon/controller/ |
| D | hip04-bootwrapper.yaml | 12 description: Bootwrapper boot method (software protocol on SMP)
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| D | sysctrl.yaml | 54 smp-offset:
119 smp-offset = <0x31c>;
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| /Documentation/locking/ |
| D | preempt-locking.rst | 13 those under SMP: concurrency and reentrancy. Thankfully, the Linux preemptible
14 kernel model leverages existing SMP locking mechanisms. Thus, the kernel
32 First, since the data is per-CPU, it may not have explicit SMP locking, but
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| /Documentation/translations/zh_CN/core-api/ |
| D | genericirq.rst | 56 - 每cpu型（针对CPU SMP）
125 - disable_irq_nosync() (SMP only)
127 - synchronize_irq() (SMP only)
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| /Documentation/devicetree/bindings/arm/mstar/ |
| D | mstar,smpctrl.yaml | 8 title: MStar/SigmaStar Armv7 SoC SMP control registers
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| /Documentation/features/core/generic-idle-thread/ |
| D | arch-support.txt | 4 # description: arch makes use of the generic SMP idle thread facility
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