Searched full:sw (Results 1 – 25 of 90) sorted by relevance
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| /Documentation/driver-api/cxl/ |
| D | access-coordinates.rst | 10 For certain CXL region construction with endpoints behind CXL switches (SW) or
40 > SW 0 SW 1 SW 2 SW 3
47 Min(SW 0 Upstream Link to RP0 BW,
50 Min(SW 1 Upstream Link to RP1 BW,
54 Min(SW 2 Upstream Link to RP2 BW,
57 Min(SW 3 Upstream Link to RP3 BW,
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| /Documentation/driver-api/ |
| D | infiniband.rst | 49 .. kernel-doc:: drivers/infiniband/sw/rdmavt/mr.c
52 .. kernel-doc:: drivers/infiniband/sw/rdmavt/rc.c
55 .. kernel-doc:: drivers/infiniband/sw/rdmavt/ah.c
58 .. kernel-doc:: drivers/infiniband/sw/rdmavt/vt.c
61 .. kernel-doc:: drivers/infiniband/sw/rdmavt/cq.c
64 .. kernel-doc:: drivers/infiniband/sw/rdmavt/qp.c
67 .. kernel-doc:: drivers/infiniband/sw/rdmavt/mcast.c
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| /Documentation/devicetree/bindings/gpio/ |
| D | spear_spics.txt | 20 * st-spics,sw-enable-bit: bit offset to enable sw control
35 st-spics,sw-enable-bit = <12>;
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| /Documentation/devicetree/bindings/ata/ |
| D | ahci-st.txt | 17 - reset-names : Associated names must be; "pwr-dwn", "sw-rst" and "pwr-rst"
32 reset-names = "pwr-dwn", "sw-rst", "pwr-rst";
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| D | mediatek,mtk-ahci.yaml | 51 - const: sw
96 reset-names = "axi", "sw", "reg";
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| /Documentation/devicetree/bindings/phy/ |
| D | phy-miphy28lp.txt | 31 - reset-names : Associated name must be "miphy-sw-rst".
66 reset-names = "miphy-sw-rst";
82 reset-names = "miphy-sw-rst";
95 reset-names = "miphy-sw-rst";
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| /Documentation/devicetree/bindings/regulator/ |
| D | ti,tps62864.yaml | 27 SW:
53 SW {
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| D | pfuze100.yaml | 42 fsl,pfuze-support-disable-sw:
68 "^sw([1-4]|[1-4][a-c]|[1-4][a-c][a-c])$":
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| /Documentation/devicetree/bindings/reset/ |
| D | nuvoton,npcm750-reset.yaml | 28 nuvoton,sw-reset-number:
52 nuvoton,sw-reset-number = <2>;
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| D | snps,hsdk-reset.txt | 10 configuration register and second for corresponding SW reset and status bits
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| /Documentation/devicetree/bindings/watchdog/ |
| D | dlg,da9062-watchdog.yaml | 25 dlg,use-sw-pm:
52 dlg,use-sw-pm;
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| D | alphascale,asm9260-wdt.yaml | 44 Specifies the reset mode of operation. If set to sw, then reset is handled
47 enum: [hw, sw, debug]
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| /Documentation/devicetree/bindings/misc/ |
| D | aspeed,ast2400-cvic.yaml | 38 copro-sw-interrupts:
59 copro-sw-interrupts = <1>;
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| /Documentation/devicetree/bindings/power/reset/ |
| D | st-reset.txt | 1 *Device-Tree bindings for ST SW reset functionality
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| /Documentation/ABI/testing/ |
| D | sysfs-bus-iio-dac | 26 Performs a SW switch to a predefined output symbol. This attribute
57 Performs a SW switch to a predefined output symbol. This attribute
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| D | sysfs-driver-hid-corsair | 5 Description: Get/set the current playback mode. "SW" for software mode
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| /Documentation/security/ |
| D | snp-tdx-threat-model.rst | 30 classified into different subtypes depending on the SW that is intended
37 CoCo, in the virtualization context, refers to a set of HW and/or SW
38 technologies that allow for stronger security guarantees for the SW running
40 confirm the trustworthiness of all SW pieces to include in its reduced
81 while in others it may be pure SW.
131 CoCo VM TCB due to its large SW attack surface. It is important to note
191 CoCo technology SW/HW protection. This includes any possible
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| /Documentation/hwmon/ |
| D | fam15h_power.rst | 102 iii. At time x, SW reads CpuSwPwrAcc MSR and samples the PTSC.
106 iv. At time y, SW reads CpuSwPwrAcc MSR and samples the PTSC.
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| /Documentation/devicetree/bindings/arm/freescale/ |
| D | fsl,imx7ulp-sim.yaml | 17 and a set of registers have been made available in DGO domain for SW use, with the
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| /Documentation/devicetree/bindings/soc/qcom/ |
| D | qcom,dcc.yaml | 15 or SW trigger. DCC is used to capture and store data for debugging purpose
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| /Documentation/networking/device_drivers/wifi/intel/ |
| D | ipw2100.rst | 178 1 SW based RF kill active (radio off)
180 3 Both HW and SW RF kill active (radio off)
186 0 If SW based RF kill active, turn the radio back on
187 1 If radio is on, activate SW based RF kill
192 If you enable the SW based RF kill and then toggle the HW
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| /Documentation/accounting/ |
| D | cgroupstats.rst | 6 https://lore.kernel.org/r/461CF883.2030308@sw.ru and implements per cgroup statistics as
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | marvell,mvebu-pinctrl.txt | 42 pmx_uart1_sw: pmx-uart1-sw {
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| /Documentation/leds/ |
| D | leds-cht-wcove.rst | 36 for both sw and hw blinking the brightness can also be changed
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| /Documentation/devicetree/bindings/thermal/ |
| D | nvidia,tegra30-tsensor.yaml | 19 Generates an interrupt to SW to lower temperature via DVFS on reaching
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