Searched full:secure (Results 1 – 25 of 189) sorted by relevance
12345678
| /Documentation/devicetree/bindings/arm/ |
| D | secure.txt | 1 * ARM Secure world bindings
4 "Normal" and "Secure". Most devicetree consumers (including the Linux
6 world or the Secure world. However some devicetree consumers are
8 visible only in the Secure address space, only in the Normal address
10 virtual machine which boots Secure firmware and wants to tell the
13 The general principle of the naming scheme for Secure world bindings
14 is that any property that needs a different value in the Secure world
15 can be supported by prefixing the property name with "secure-". So for
16 instance "secure-foo" would override "foo". For property names with
17 a vendor prefix, the Secure variant of "vendor,foo" would be
[all …]
|
| /Documentation/devicetree/bindings/arm/amlogic/ |
| D | amlogic,meson-gx-ao-secure.yaml | 5 $id: http://devicetree.org/schemas/arm/amlogic/amlogic,meson-gx-ao-secure.yaml#
15 secure firmware.
22 const: amlogic,meson-gx-ao-secure
30 - const: amlogic,meson-gx-ao-secure
34 - amlogic,a4-ao-secure
35 - amlogic,c3-ao-secure
36 - amlogic,s4-ao-secure
37 - amlogic,t7-ao-secure
38 - const: amlogic,meson-gx-ao-secure
58 ao-secure@140 {
[all …]
|
| D | amlogic,meson-mx-secbus2.yaml | 16 The registers can be accessed directly when not running in "secure mode".
17 When "secure mode" is enabled then these registers have to be accessed
18 through secure monitor calls.
|
| /Documentation/devicetree/bindings/crypto/ |
| D | inside-secure,safexcel.yaml | 4 $id: http://devicetree.org/schemas/crypto/inside-secure,safexcel.yaml#
7 title: Inside Secure SafeXcel cryptographic engine
15 - const: inside-secure,safexcel-eip197b
16 - const: inside-secure,safexcel-eip197d
17 - const: inside-secure,safexcel-eip97ies
18 - const: inside-secure,safexcel-eip197
19 description: Equivalent of inside-secure,safexcel-eip197b
21 - const: inside-secure,safexcel-eip97
22 description: Equivalent of inside-secure,safexcel-eip97ies
75 compatible = "inside-secure,safexcel-eip197b";
|
| /Documentation/devicetree/bindings/mailbox/ |
| D | ti,secure-proxy.yaml | 4 $id: http://devicetree.org/schemas/mailbox/ti,secure-proxy.yaml#
7 title: Texas Instruments' Secure Proxy
13 The Texas Instruments' secure proxy is a mailbox controller that has
25 const: ti,am654-secure-proxy
30 Contains the secure proxy thread ID used for the specific transfer path.
48 secure proxy thread in the form 'rx_<PID>'.
54 Contains the interrupt information for the Rx interrupt path for secure
71 compatible = "ti,am654-secure-proxy";
|
| D | arm,mhu.yaml | 19 be a 'Secure' resource, hence can't be used by Linux running NS.
62 - description: low-priority non-secure
63 - description: high-priority non-secure
64 - description: Secure
101 <0 37 4>; /* Secure */
133 <0 37 4>; /* Secure */
|
| /Documentation/devicetree/bindings/arm/samsung/ |
| D | samsung-secure-firmware.yaml | 4 $id: http://devicetree.org/schemas/arm/samsung/samsung-secure-firmware.yaml#
7 title: Samsung Exynos Secure Firmware
15 - const: samsung,secure-firmware
19 Address of non-secure SYSRAM used for communication with firmware.
31 compatible = "samsung,secure-firmware";
|
| /Documentation/arch/powerpc/ |
| D | ultravisor.rst | 15 POWER 9 that enables Secure Virtual Machines (SVMs). DD2.3 chips
56 process is running in secure mode, MSR(S) bit 41. MSR(S)=1, process
57 is in secure mode, MSR(s)=0 process is in normal mode.
63 the VM it is returning to is secure.
73 **Secure Mode MSR Settings**
101 * Memory is partitioned into secure and normal memory. Only processes
102 that are running in secure mode can access secure memory.
104 * The hardware does not allow anything that is not running secure to
105 access secure memory. This means that the Hypervisor cannot access
110 * I/O systems are not allowed to directly address secure memory. This
[all …]
|
| /Documentation/devicetree/bindings/nvmem/ |
| D | st,stm32-romem.yaml | 40 st,non-secure-otp:
42 This property explicits a factory programmed area that both secure
43 and non-secure worlds can access. It is needed when, by default, the
44 related area can only be reached by the secure world.
69 st,non-secure-otp;
|
| D | amlogic,meson-gxbb-efuse.yaml | 27 secure-monitor:
28 description: phandle to the secure-monitor node
37 - secure-monitor
48 secure-monitor = <&sm>;
|
| D | qcom,sec-qfprom.yaml | 7 title: Qualcomm Technologies Inc, Secure QFPROM Efuse
14 protected from non-secure access. In such situations, the OS have to use
15 secure calls to read the region.
30 - description: The secure qfprom corrected region.
|
| /Documentation/devicetree/bindings/power/ |
| D | amlogic,meson-sec-pwrc.yaml | 9 title: Amlogic Meson Secure Power Domains
15 Secure Power Domains used in Meson A1/C1/S4 & C3/T7 SoCs, and should be the child node
16 of secure-monitor.
39 secure-monitor {
|
| /Documentation/devicetree/bindings/thermal/ |
| D | amlogic,thermal.yaml | 38 amlogic,ao-secure:
39 description: phandle to the ao-secure syscon
50 - amlogic,ao-secure
63 amlogic,ao-secure = <&sec_AO>;
|
| /Documentation/devicetree/bindings/firmware/ |
| D | intel,stratix10-svc.txt | 4 processor system (HPS) and Secure Device Manager (SDM). When the FPGA is
10 communication with SDM, only the secure world of software (EL3, Exception
18 driver also manages secure monitor call (SMC) to communicate with secure monitor
28 smc - Secure Monitor Call
|
| D | brcm,kona-smc.yaml | 7 title: Broadcom Kona family Secure Monitor bounce buffer
10 A bounce buffer used for non-secure to secure communications.
|
| D | amlogic,meson-gxbb-sm.yaml | 7 title: Amlogic Secure Monitor (SM)
10 In the Amlogic SoCs the Secure Monitor code is used to provide access to the
36 secure-monitor {
|
| /Documentation/devicetree/bindings/rng/ |
| D | omap_rng.yaml | 7 title: OMAP SoC and Inside-Secure HWRNG Module
17 - inside-secure,safexcel-eip76
50 - inside-secure,safexcel-eip76
75 compatible = "inside-secure,safexcel-eip76";
|
| D | ti,omap-rom-rng.yaml | 14 Secure SoCs may provide RNG via secure ROM calls like Nokia N900 does.
15 The implementation can depend on the SoC secure ROM used.
|
| /Documentation/tee/ |
| D | amd-tee.rst | 8 TEE environment is provided by AMD Secure Processor.
10 The AMD Secure Processor (formerly called Platform Security Processor or PSP)
21 User space (Kernel space) | AMD Secure Processor (PSP)
44 At the lowest level (in x86), the AMD Secure Processor (ASP) driver uses the
47 the secure processor and return results to AMD-TEE driver. The interface
48 between AMD-TEE driver and AMD Secure Processor driver can be found in [1].
64 AMD-TEE Trusted OS is the firmware running on AMD Secure Processor.
79 talk to AMD's TEE. AMD's TEE provides a secure environment for loading, opening
|
| D | op-tee.rst | 23 separate secure co-processor.
36 User space Kernel Secure world
56 RPC (Remote Procedure Call) are requests from secure world to kernel driver
74 There are two kinds of notifications that secure world can use to make
79 2. Asynchronous notifications delivered with a combination of a non-secure
80 edge-triggered interrupt and a fast call from the non-secure interrupt
84 this is only usable when secure world is entered with a yielding call via
85 ``OPTEE_SMC_CALL_WITH_ARG``. This excludes such notifications from secure
88 An asynchronous notification is delivered via a non-secure edge-triggered
98 building block for OP-TEE OS in secure world to implement the top half and
|
| /Documentation/devicetree/bindings/arm/aspeed/ |
| D | aspeed,sbc.yaml | 8 title: ASPEED Secure Boot Controller
15 The ASPEED SoCs have a register bank for interacting with the secure boot
34 sbc: secure-boot-controller@1e6f2000 {
|
| /Documentation/devicetree/bindings/iommu/ |
| D | qcom,iommu.yaml | 16 to non-secure vs secure interrupt line.
50 qcom,iommu-secure-id:
53 The SCM secure ID of the IOMMU instance.
114 qcom,iommu-secure-id = <17>;
|
| /Documentation/devicetree/bindings/arm/tegra/ |
| D | nvidia,tegra194-cbb.yaml | 59 CCPLEX receives secure or nonsecure interrupt depending on error type.
60 A secure interrupt is received for SEC(firewall) & SLV errors and a
61 non-secure interrupt is received for TMO & DEC errors.
63 - description: non-secure interrupt
64 - description: secure interrupt
|
| /Documentation/virt/kvm/s390/ |
| D | s390-pv.rst | 20 The Ultravisor will secure and decrypt the guest's boot memory
70 The control structures associated with SIE provide the Secure
72 Secure Interception General Register Save Area. Guest GRs and most of
75 GRs are put into / retrieved from the Secure Interception General
88 The Secure Instruction Data Area contains instruction storage
99 There are two types of SIE secure instruction intercepts: the normal
100 and the notification type. Normal secure instruction intercepts will
|
| /Documentation/ABI/testing/ |
| D | sysfs-secvar | 5 secureboot, thereby secure variables. It exposes interface
6 for reading/writing the secure variables
11 Description: This directory lists all the secure variables that are supported
32 Description: Each secure variable is represented as a directory named as
60 defined by the secure variable implementation. All data is in
|
12345678