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| /Documentation/devicetree/bindings/pinctrl/ |
| D | pinctrl-single.yaml | 4 $id: http://devicetree.org/schemas/pinctrl/pinctrl-single.yaml#
7 title: Generic Pin Controller with a Single Register for One or More Pins
13 Some pin controller devices use a single register for one or more pins. The
22 - pinctrl-single
23 - pinconf-single
35 - const: pinctrl-single
57 pinctrl-single,bit-per-mux:
61 pinctrl-single,function-mask:
65 pinctrl-single,function-off:
69 pinctrl-single,register-width:
[all …]
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| /Documentation/ABI/testing/ |
| D | debugfs-dell-wmi-ddv | 12 - fan type (single byte)
28 - thermal type (single byte)
29 - current temperature (single byte)
30 - min. temperature (single byte)
31 - max. temperature (single byte)
32 - unknown field (single byte)
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| D | sysfs-bus-intel_th-devices-msc | 13 - "single", for contiguous buffer mode (high-order alloc);
27 Description: (RW) Configure MSC buffer size for "single" or "multi" modes.
29 In single mode, this is a single number of pages, has to be
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| /Documentation/devicetree/bindings/iio/adc/ |
| D | adc.yaml | 41 single-channel:
44 When devices combine single-ended and differential channels, allow the
45 channel for a single element to be specified, independent of reg (as for
53 single-ended or pseudo-differential inputs. This property can be used
54 in addition to single-channel to signal software that this channel is
57 The input pair is specified by setting single-channel to the positive
79 - single-channel
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| D | ti,ads1119.yaml | 13 The TI ADS1119 is a precision 16-bit ADC over I2C that offers single-ended and
78 single-channel:
80 Single-ended input channels AIN0, AIN1, AIN2 and AIN3.
88 - single-channel
122 single-channel = <0>;
132 single-channel = <3>;
137 single-channel = <1>;
142 single-channel = <2>;
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| /Documentation/hwmon/ |
| D | pcf8591.rst | 29 The PCF8591 has 4 analog inputs programmable as single-ended or
32 - mode 0 : four single ended inputs
33 Pins AIN0 to AIN3 are single ended inputs for channels 0 to 3
39 - mode 2 : single ended and differential mixed
40 Pins AIN0 and AIN1 are single ended inputs for channels 0 and 1
59 - 0 = four single ended inputs
61 - 2 = single ended and differential mixed
89 from 0 to 255 for single ended inputs and -128 to +127 for differential inputs
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| /Documentation/devicetree/bindings/edac/ |
| D | socfpga-eccmgr.txt | 3 The ECC Manager counts and corrects single bit errors and counts/handles
19 - interrupts : Should be single bit error interrupt, then double bit error
27 - interrupts : Should be single bit error interrupt, then double bit error
63 - interrupts : Should be single bit error interrupt, then double bit error
75 - interrupts : Should be single bit error interrupt, then double bit error
82 - interrupts : Should be single bit error interrupt, then double bit error
90 - interrupts : Should be single bit error interrupt, then double bit error
98 - interrupts : Should be single bit error interrupt, then double bit error
106 - interrupts : Should be single bit error interrupt, then double bit error
114 - interrupts : Should be single bit error interrupt, then double bit error
[all …]
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| /Documentation/userspace-api/media/v4l/ |
| D | planar-apis.rst | 6 Single- and multi-planar APIs
20 depending on whether single- or multi-planar API is being used. An
34 can handle all single-planar formats as well (as long as they are passed
35 in multi-planar API structures), while the single-planar API cannot
39 Calls that distinguish between single and multi-planar APIs
45 single- and multi-planar formats.
52 FourCC codes from the existing single-planar ones.
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| /Documentation/devicetree/bindings/sound/ |
| D | pcm3060.txt | 14 - ti,out-single-ended: "true" if output is single-ended;
22 ti,out-single-ended = "true";
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| D | cs42l52.txt | 23 Single-ended input. Single-ended mode allows for MIC1 or MIC2 muxing for input.
27 Single-ended input. Single-ended mode allows for MIC1 or MIC2 muxing for input.
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| D | max98373.txt | 24 - maxim,interleave-mode : For cases where a single combined channel
26 to share a single data output channel on alternating frames.
28 on a single output channel.
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| /Documentation/tools/rtla/ |
| D | rtla-hwnoise.rst | 48 …CPU Period Runtime Noise % CPU Aval Max Noise Max Single HW NMI
65 single period, and the *Max Single* is the maximum single noise seen.
72 for the application. In the worst single period, the CPU caused *4 us* of
73 noise to the application, but it was certainly caused by more than one single
74 noise, as the *Max Single* noise was of *3 us*. The CPU has *HW noise,* at a
87 …CPU Period Runtime Noise % CPU Aval Max Noise Max Single HW NMI
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| /Documentation/devicetree/bindings/media/ |
| D | renesas,isp.yaml | 53 Single endpoint describing the R-Car VIN connected to output port 0.
58 Single endpoint describing the R-Car VIN connected to output port 1.
63 Single endpoint describing the R-Car VIN connected to output port 2.
68 Single endpoint describing the R-Car VIN connected to output port 3.
73 Single endpoint describing the R-Car VIN connected to output port 4.
78 Single endpoint describing the R-Car VIN connected to output port 5.
83 Single endpoint describing the R-Car VIN connected to output port 6.
88 Single endpoint describing the R-Car VIN connected to output port 7.
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| /Documentation/devicetree/bindings/iio/accel/ |
| D | lis302.txt | 23 - st,click-single-{x,y,z}: if present, tells the device to issue an
24 interrupt on single click events on the
74 st,click-single-x;
75 st,click-single-y;
76 st,click-single-z;
98 st,click-single-x;
99 st,click-single-y;
100 st,click-single-z;
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| /Documentation/devicetree/bindings/mux/ |
| D | mux-consumer.yaml | 16 mux-ctrl-list ::= <single-mux-ctrl> [mux-ctrl-list]
17 single-mux-ctrl ::= <mux-ctrl-phandle> [mux-ctrl-specifier]
40 If the mux controller chip only provides a single mux controller, the
54 Devices that use more than a single mux controller can use the
60 Devices that use more than a single multiplexer state can use the
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| /Documentation/devicetree/bindings/regulator/ |
| D | maxim,max77686.yaml | 30 Properties for single LDO regulator.
43 Properties for single LDO regulator.
60 Properties for single BUCK regulator.
72 Properties for single BUCK regulator.
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| D | dlg,da9121.yaml | 13 Dialog Semiconductor DA9121 Single-channel 10A double-phase buck converter
14 Dialog Semiconductor DA9122 Double-channel 5A single-phase buck converter
15 Dialog Semiconductor DA9220 Double-channel 3A single-phase buck converter
16 Dialog Semiconductor DA9217 Single-channel 6A double-phase buck converter
17 Dialog Semiconductor DA9130 Single-channel 10A double-phase buck converter
18 Dialog Semiconductor DA9131 Double-channel 5A single-phase buck converter
19 Dialog Semiconductor DA9132 Double-channel 3A single-phase buck converter
20 Dialog Semiconductor DA9141 Single-channel 40A quad-phase buck converter
21 Dialog Semiconductor DA9142 Single-channel 20A double-phase buck converter
95 Properties for a single BUCK regulator
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| D | samsung,s2mps14.yaml | 28 Properties for single LDO regulator.
38 Properties for single LDO regulator.
56 Properties for single BUCK regulator.
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| /Documentation/devicetree/bindings/display/bridge/ |
| D | thine,thc63lvd1024.yaml | 15 streams to parallel data outputs. The chip supports single/dual input/output
19 Single or dual operation mode, output data mapping and DDR output modes are
30 The device can operate in single or dual input and output modes.
32 When operating in single input mode, all pixels are received on port@0,
37 When operating in single output mode all pixels are output from the first
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| D | lontium,lt9211.yaml | 13 The LT9211 are bridge devices which convert Single/Dual-Link DSI/LVDS
14 or Single DPI to Single/Dual-Link DSI/LVDS or Single DPI.
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| /Documentation/fb/ |
| D | viafb.rst | 67 - 0 : Resolution: 640x480, Channel: single, Dithering: Enable
68 - 1 : Resolution: 800x600, Channel: single, Dithering: Enable
69 - 2 : Resolution: 1024x768, Channel: single, Dithering: Enable (default)
70 - 3 : Resolution: 1280x768, Channel: single, Dithering: Enable
75 - 8 : Resolution: 800x480, Channel: single, Dithering: Enable
77 - 10: Resolution: 1024x768, Channel: single, Dithering: Disable
79 - 12: Resolution: 1280x768, Channel: single, Dithering: Disable
83 - 16: Resolution: 1366x768, Channel: single, Dithering: Disable
84 - 17: Resolution: 1024x600, Channel: single, Dithering: Enable
86 - 19: Resolution: 1280x800, Channel: single, Dithering: Enable
[all …]
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| /Documentation/filesystems/ |
| D | inotify.rst | 45 There are other good arguments. With a single fd, there is a single
46 item to block on, which is mapped to a single queue of events. The single
52 which happened first. A single queue trivially gives you ordering. Such
57 versus just one. It is a lot messier in the kernel. A single, linear
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| /Documentation/devicetree/bindings/arm/omap/ |
| D | ctrl.txt | 11 [1] Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml
48 "pinctrl-single";
54 pinctrl-single,register-width = <16>;
55 pinctrl-single,function-mask = <0xff1f>;
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| /Documentation/devicetree/bindings/hwmon/ |
| D | ti,ina3221.yaml | 20 ti,single-shot:
22 This chip has two power modes: single-shot (chip takes one measurement
25 hardware monitor type device, but the single-shot mode is more power-
29 If this property is present, the single-shot mode will be used, instead
64 summation control function. This function adds the single
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| /Documentation/ |
| D | atomic_bitops.txt | 6 operating on single bits in a bitmap that are atomic.
12 The single bit operations are:
67 Since a platform only has a single means of achieving atomic operations
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