Searched +full:soc +full:- +full:ip (Results 1 – 25 of 174) sorted by relevance
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| /Documentation/devicetree/bindings/sifive/ |
| D | sifive-blocks-ip-versioning.txt | 1 DT compatible string versioning for SiFive open-source IP blocks
4 strings for open-source SiFive IP blocks. HDL for these IP blocks
7 https://github.com/sifive/sifive-blocks
9 IP block-specific DT compatible strings are contained within the HDL,
10 in the form "sifive,<ip-block-name><integer version number>".
14 https://github.com/sifive/sifive-blocks/blob/v1.0/src/main/scala/devices/uart/UART.scala#L43
16 Until these IP blocks (or IP integration) support version
17 auto-discovery, the maintainers of these IP blocks intend to increment
19 interface to these IP blocks changes, or when the functionality of the
20 underlying IP blocks changes in a way that software should be aware of.
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| /Documentation/devicetree/bindings/rtc/ |
| D | rtc-omap.txt | 4 - compatible:
5 - "ti,da830-rtc" - for RTC IP used similar to that on DA8xx SoC family.
6 - "ti,am3352-rtc" - for RTC IP used similar to that on AM335x SoC family.
7 This RTC IP has special WAKE-EN Register to enable
11 - "ti,am4372-rtc" - for RTC IP used similar to that on AM437X SoC family.
12 - reg: Address range of rtc register set
13 - interrupts: rtc timer, alarm interrupts in order
16 - system-power-controller: whether the rtc is controlling the system power
18 - clocks: Any internal or external clocks feeding in to rtc
19 - clock-names: Corresponding names of the clocks
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| /Documentation/devicetree/bindings/soc/mediatek/ |
| D | mediatek,pwrap.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/mediatek/mediatek,pwrap.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Flora Fu <flora.fu@mediatek.com>
11 - Alexandre Mergnat <amergnat@baylibre.com>
16 inside the SoC. The communication between the SoC and the PMIC can
20 IP Pairing
22 On MT8135 the pins of some SoC internal peripherals can be on the PMIC.
25 are marked with "IP Pairing". These are optional on SoCs which do not support
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| /Documentation/devicetree/bindings/clock/ti/ |
| D | dra7-atl.txt | 1 Device Tree Clock bindings for ATL (Audio Tracking Logic) of DRA7 SoC.
3 The ATL IP is used to generate clock to be used to synchronize baseband and
4 audio codec. A single ATL IP provides four ATL clock instances sharing the same
7 signals - can compensate the drift between the two ws signal.
10 internally within the SoC or external components) two sets of bindings is needed:
16 Since the clock instances are part of a single IP this binding is used as a node
17 for the DT clock tree, the IP driver is needed to handle the actual configuration
18 of the IP.
20 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
23 - compatible : shall be "ti,dra7-atl-clock"
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| /Documentation/devicetree/bindings/display/ |
| D | st,stih4xx.txt | 3 - sti-vtg: video timing generator
5 - compatible: "st,vtg"
6 - reg: Physical base address of the IP registers and length of memory mapped region.
8 - interrupts : VTG interrupt number to the CPU.
9 - st,slave: phandle on a slave vtg
11 - sti-vtac: video timing advanced inter dye communication Rx and TX
13 - compatible: "st,vtac-main" or "st,vtac-aux"
14 - reg: Physical base address of the IP registers and length of memory mapped region.
15 - clocks: from common clock binding: handle hardware IP needed clocks, the
16 number of clocks may depend of the SoC type.
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| /Documentation/devicetree/bindings/i2c/ |
| D | opencores,i2c-ocores.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/opencores,i2c-ocores.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peter Korsgaard <peter@korsgaard.com>
11 - Andrew Lunn <andrew@lunn.ch>
14 - $ref: /schemas/i2c/i2c-controller.yaml#
19 - items:
20 - enum:
21 - sifive,fu740-c000-i2c # Opencore based IP block FU740-C000 SoC
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| D | microchip,corei2c.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Daire McNamara <daire.mcnamara@microchip.com>
13 - $ref: /schemas/i2c/i2c-controller.yaml#
18 - items:
19 - const: microchip,mpfs-i2c # Microchip PolarFire SoC compatible SoCs
20 - const: microchip,corei2c-rtl-v7 # Microchip Fabric based i2c IP core
21 - const: microchip,corei2c-rtl-v7 # Microchip Fabric based i2c IP core
32 clock-frequency:
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| /Documentation/gpu/amdgpu/ |
| D | driver-core.rst | 9 "IPs" (Intellectual Property blocks). Each IP encapsulates certain
13 the initialization and operation of each IP. There are also a bunch
15 Those end up getting lumped into the common stuff in the soc files.
16 The soc files (e.g., vi.c, soc15.c nv.c) contain code for aspects of
17 the SoC itself rather than specific IPs. E.g., things like GPU resets
18 and register access functions are SoC dependent.
32 This was a dedicated IP on older pre-vega chips, but has since
43 their interrupts into this IP and it aggregates them into a set of
48 This handles security policy for the SoC and executes trusted
53 SoC. The driver interacts with it to control power management
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| /Documentation/devicetree/bindings/net/ |
| D | cdns,macb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nicolas Ferre <nicolas.ferre@microchip.com>
11 - Claudiu Beznea <claudiu.beznea@microchip.com>
16 - items:
17 - enum:
18 - cdns,at91rm9200-emac # Atmel at91rm9200 SoC
19 - const: cdns,emac # Generic
21 - items:
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| D | snps,dwc-qos-ethernet.txt | 1 * Synopsys DWC Ethernet QoS IP version 4.10 driver (GMAC)
7 IP block. The IP supports multiple options for bus type, clocking and reset
13 - compatible: One of:
14 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
15 Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
16 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"
17 Represents the IP core when integrated into the NVIDIA Tegra186 SoC.
18 - "snps,dwc-qos-ethernet-4.10"
20 "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be
22 - reg: Address and length of the register set for the device
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | brcm,iproc-gpio.txt | 5 - compatible:
6 "brcm,iproc-gpio" for the generic iProc based GPIO controller IP that
7 supports full-featured pinctrl and GPIO functions used in various iProc
10 May contain an SoC-specific compatibility string to accommodate any
11 SoC-specific features
13 "brcm,cygnus-ccm-gpio", "brcm,cygnus-asiu-gpio", or
14 "brcm,cygnus-crmu-gpio" for Cygnus SoCs
16 "brcm,iproc-nsp-gpio" for the iProc NSP SoC that has drive strength support
19 "brcm,iproc-stingray-gpio" for the iProc Stingray SoC that has the general
20 pinctrl support completely disabled in this IP block. In Stingray, a
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| /Documentation/devicetree/bindings/media/ |
| D | samsung,exynos4210-fimc.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/media/samsung,exynos4210-fimc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung S5P/Exynos SoC Fully Integrated Mobile Camera
10 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
11 - Sylwester Nawrocki <s.nawrocki@samsung.com>
15 fimc<n>, where <n> is an integer specifying the IP block instance.
20 - samsung,exynos4210-fimc
21 - samsung,exynos4212-fimc
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| D | st,st-hva.txt | 1 st-hva: multi-format video encoder for STMicroelectronics SoC.
4 - compatible: should be "st,st-hva".
5 - reg: HVA physical address location and length, esram address location and
7 - reg-names: names of the registers listed in registers property in the same
9 - interrupts: HVA interrupt number.
10 - clocks: from common clock binding: handle hardware IP needed clocks, the
11 number of clocks may depend on the SoC type.
12 See ../clock/clock-bindings.txt for details.
13 - clock-names: names of the clocks listed in clocks property in the same order.
17 compatible = "st,st-hva";
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| D | st,stih4xx.txt | 3 bdisp: 2D blitter for STMicroelectronics SoC.
6 - compatible: should be "st,stih407-bdisp".
7 - reg: BDISP physical address location and length.
8 - interrupts: BDISP interrupt number.
9 - clocks: from common clock binding: handle hardware IP needed clocks, the
10 number of clocks may depend on the SoC type.
11 See ../clocks/clock-bindings.txt for details.
12 - clock-names: names of the clocks listed in clocks property in the same order.
17 compatible = "st,stih407-bdisp";
20 clock-names = "bdisp";
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| D | allegro,al5e.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allegro DVT Video IP Codecs
10 - Michael Tretter <m.tretter@pengutronix.de>
12 description: |-
13 Allegro DVT video IP codecs present in the Xilinx ZynqMP SoC. The IP core may
14 either be a H.264/H.265 encoder or H.264/H.265 decoder ip core.
23 - items:
24 - const: allegro,al5e-1.1
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| /Documentation/devicetree/bindings/arm/samsung/ |
| D | samsung-soc.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/arm/samsung/samsung-soc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung S3C, S5P and Exynos SoC compatibles naming convention
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 Guidelines for new compatibles for SoC blocks/components.
15 samsung,SoC-IP
18 samsung,exynos5433-cmu-isp
23 pattern: "^samsung,.*(s3c|s5pv|exynos)[0-9a-z]+.*$"
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| /Documentation/devicetree/bindings/soc/imx/ |
| D | fsl,aips-bus.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl,aips-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: i.MX AHB to IP Bridge
10 - Peng Fan <peng.fan@nxp.com>
14 AHB bus and peripherals with the lower bandwidth IP Slave (IPS)
21 const: fsl,aips-bus
23 - compatible
28 - const: fsl,aips-bus
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| /Documentation/accel/ |
| D | introduction.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 accelerators in a common way to user-space and provide a common set of
11 These devices can be either stand-alone ASICs or IP blocks inside an SoC/GPU.
13 Machine-Learning (ML) and/or Deep-Learning (DL) computations, the accel layer
19 - Edge AI - doing inference at an edge device. It can be an embedded ASIC/FPGA,
20 or an IP inside a SoC (e.g. laptop web camera). These devices
23 - Inference data-center - single/multi user devices in a large server. This
24 type of device can be stand-alone or an IP inside a SoC or a GPU. It will
25 have on-board DRAM (to hold the DL topology), DMA engines and
26 command submission queues (either kernel or user-space queues).
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| /Documentation/devicetree/bindings/clock/ |
| D | mediatek,mt8365-sys-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/mediatek,mt8365-sys-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Markus Schneider-Pargmann <msp@baylibre.com>
13 The apmixedsys module provides most of PLLs which generated from SoC 26m.
14 The topckgen provides dividers and muxes which provides the clock source to other IP blocks.
15 The infracfg_ao and pericfg_ao provides clock gate in peripheral and infrastructure IP blocks.
20 - enum:
21 - mediatek,mt8365-topckgen
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| D | mediatek,mt8188-sys-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/mediatek,mt8188-sys-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Garmin Chang <garmin.chang@mediatek.com>
14 PLLs -->
15 dividers -->
17 -->
20 The apmixedsys provides most of PLLs which generated from SoC 26m.
21 The topckgen provides dividers and muxes which provide the clock source to other IP blocks.
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| D | mediatek,mt8186-sys-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/mediatek,mt8186-sys-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chun-Jie Chen <chun-jie.chen@mediatek.com>
14 PLLs -->
15 dividers -->
17 -->
20 The apmixedsys provides most of PLLs which generated from SoC 26m.
21 The topckgen provides dividers and muxes which provide the clock source to other IP blocks.
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| /Documentation/devicetree/bindings/spi/ |
| D | brcm,spi-bcm-qspi.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/spi/brcm,spi-bcm-qspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kamal Dasu <kdasu.kdev@gmail.com>
11 - Rafał Miłecki <rafal@milecki.pl>
15 BRCMSTB (BCM7XXX), Cygnus, NSP and NS2. The Broadcom Master SPI hw IP consists
18 BSPI : Broadcom SPI in combination with the MSPI hw IP provides acceleration
20 io with 3-byte and 4-byte addressing support.
22 Supported Broadcom SoCs have one instance of MSPI+BSPI controller IP.
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| /Documentation/devicetree/bindings/devfreq/event/ |
| D | samsung,exynos-ppmu.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/devfreq/event/samsung,exynos-ppmu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos SoC PPMU (Platform Performance Monitoring Unit)
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
14 The Samsung Exynos SoC has PPMU (Platform Performance Monitoring Unit) for
15 each IP. PPMU provides the primitive values to get performance data. These
16 PPMU events provide information of the SoC's behaviors so that you may use to
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| /Documentation/userspace-api/media/ |
| D | glossary.rst | 1 .. SPDX-License-Identifier: GPL-2.0 OR GFDL-1.1-no-invariants-or-later
58 **Field-programmable Gate Array**
63 See https://en.wikipedia.org/wiki/Field-programmable_gate_array.
67 :term:`SPI` device, or an :term:`IP Block` inside an
68 :term:`SoC` or :term:`FPGA`.
72 together make a larger user-facing functional peripheral. For
73 instance, the :term:`SoC` :term:`ISP` :term:`IP Block`
80 **Inter-Integrated Circuit**
82 A multi-master, multi-slave, packet switched, single-ended,
84 like sub-device hardware components.
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| /Documentation/devicetree/bindings/mmc/ |
| D | marvell,xenon-sdhci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/marvell,xenon-sdhci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 mmc-controller.yaml and the properties used by the Xenon implementation.
13 Multiple SDHCs might be put into a single Xenon IP, to save size and cost.
20 - Ulf Hansson <ulf.hansson@linaro.org>
25 - enum:
26 - marvell,armada-cp110-sdhci
27 - marvell,armada-ap806-sdhci
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