Searched +full:soc +full:- +full:s (Results 1 – 25 of 465) sorted by relevance
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| /Documentation/ABI/testing/ |
| D | sysfs-devices-soc | 5 The /sys/devices/ directory contains a sub-directory for each
6 System-on-Chip (SoC) device on a running platform. Information
7 regarding each SoC can be obtained by reading sysfs files. This
10 The directory created for each SoC will also house information
12 It has been agreed that if an SoC device exists, its supported
13 devices would be better suited to appear as children of that SoC.
19 Read-only attribute common to all SoCs. Contains the SoC machine
26 Read-only attribute common to all SoCs. Contains SoC family name
30 this will contain the JEDEC JEP106 manufacturer’s identification
34 This manufacturer’s identification code is defined by one
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| D | sysfs-driver-tegra-fuse | 1 What: /sys/devices/*/<our-device>/fuse
4 Description: read-only access to the efuses on Tegra20, Tegra30, Tegra114
5 and Tegra124 SoC's from NVIDIA. The efuses contain write once
11 Tegra SoC's
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| /Documentation/devicetree/bindings/ptp/ |
| D | brcm,ptp-dte.txt | 4 - compatible: should contain the core compatibility string
5 and the SoC compatibility string. The SoC
6 compatibility string is to handle SoC specific
9 "brcm,ptp-dte"
10 SoC compatibility strings:
11 "brcm,iproc-ptp-dte" - for iproc based SoC's
12 - reg: address and length of the DTE block's NCO registers
16 ptp: ptp-dte@180af650 {
17 compatible = "brcm,iproc-ptp-dte", "brcm,ptp-dte";
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| /Documentation/devicetree/bindings/power/reset/ |
| D | keystone-reset.txt | 3 This node is intended to allow SoC reset in case of software reset
7 SoC. Each watchdog timer event input is connected to the Reset Mux
14 - compatible: ti,keystone-reset
16 - ti,syscon-pll: phandle/offset pair. The phandle to syscon used to
20 - ti,syscon-dev: phandle/offset pair. The phandle to syscon used to
26 - ti,soft-reset: Boolean option indicating soft reset.
29 - ti,wdt-list: WDT list that can cause SoC reset. It's not related
30 to WDT driver, it's just needed to enable a SoC related
31 reset that's triggered by one of WDTs. The list is
33 begins from 0 to 3, as keystone can contain up to 4 SoC
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | fsl,imx-pinctrl.txt | 10 Please refer to pinctrl-bindings.txt in this directory for details of the
18 such as pull-up, open drain, drive strength, etc.
21 - compatible: "fsl,<soc>-iomuxc"
22 Please refer to each fsl,<soc>-pinctrl.txt binding doc for supported SoCs.
25 - fsl,pins: each entry consists of 6 integers and represents the mux and config
28 imx*-pinfunc.h under device tree source folder. The last integer CONFIG is
29 the pad setting value like pull-up on this pin. And that's why fsl,pins entry
41 Please refer to each fsl,<soc>-pinctrl,txt binding doc for SoC specific part
45 Some requirements for using fsl,imx-pinctrl binding:
47 what pinmux functions this SoC supports.
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| D | brcm,iproc-gpio.txt | 5 - compatible:
6 "brcm,iproc-gpio" for the generic iProc based GPIO controller IP that
7 supports full-featured pinctrl and GPIO functions used in various iProc
10 May contain an SoC-specific compatibility string to accommodate any
11 SoC-specific features
13 "brcm,cygnus-ccm-gpio", "brcm,cygnus-asiu-gpio", or
14 "brcm,cygnus-crmu-gpio" for Cygnus SoCs
16 "brcm,iproc-nsp-gpio" for the iProc NSP SoC that has drive strength support
19 "brcm,iproc-stingray-gpio" for the iProc Stingray SoC that has the general
23 - reg:
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| /Documentation/devicetree/bindings/clock/ |
| D | microchip,mpfs-ccc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/microchip,mpfs-ccc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip PolarFire SoC Fabric Clock Conditioning Circuitry
10 - Conor Dooley <conor.dooley@microchip.com>
13 Microchip PolarFire SoC has 4 Clock Conditioning Circuitry blocks. Each of
15 the FPGA. For more information see "PolarFire SoC FPGA Clocking Resources" at:
16 https://onlinedocs.microchip.com/pr/GUID-8F0CC4C0-0317-4262-89CA-CE7773ED1931-en-US-1/index.html
20 const: microchip,mpfs-ccc
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| D | intel,cgu-lgm.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/intel,cgu-lgm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Intel Lightning Mountain SoC's Clock Controller(CGU)
10 - Rahul Tanwar <rahul.tanwar@linux.intel.com>
13 Lightning Mountain(LGM) SoC's Clock Generation Unit(CGU) driver provides
17 Please refer to include/dt-bindings/clock/intel,lgm-clk.h header file, it
23 const: intel,cgu-lgm
28 '#clock-cells':
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| /Documentation/i2c/busses/ |
| D | i2c-i801.rst | 2 Kernel driver i2c-i801
7 * Intel 82801AA and 82801AB (ICH and ICH0 - part of the
9 * Intel 82801BA (ICH2 - part of the '815E' chipset)
27 * Intel Avoton (SOC)
31 * Intel BayTrail (SOC)
32 * Intel Braswell (SOC)
35 * Intel DNV (SOC)
36 * Intel Broxton (SOC)
38 * Intel Gemini Lake (SOC)
45 * Intel Jasper Lake (SOC)
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| /Documentation/devicetree/bindings/powerpc/fsl/ |
| D | mpc5121-psc.txt | 4 ----------------
7 are specified by fsl,mpc5121-psc-uart nodes in the
8 fsl,mpc5121-immr SoC node. Additionally the PSC FIFO
9 Controller node fsl,mpc5121-psc-fifo is required there:
11 fsl,mpc512x-psc-uart nodes
12 --------------------------
15 - compatible : Should contain "fsl,<soc>-psc-uart" and "fsl,<soc>-psc"
16 Supported <soc>s: mpc5121, mpc5125
17 - reg : Offset and length of the register set for the PSC device
18 - interrupts : <a b> where a is the interrupt number of the
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| /Documentation/devicetree/bindings/hwmon/ |
| D | amd,sbrmi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 Sideband Remote Management Interface (SB-RMI) compliant
9 AMD SoC power device.
12 - Akshay Gupta <Akshay.Gupta@amd.com>
15 SB Remote Management Interface (SB-RMI) is an SMBus compatible
16 interface that reports AMD SoC's Power (normalized Power) using,
17 Mailbox Service Request and resembles a typical 8-pin remote power
18 sensor's I2C interface to BMC. The power attributes in hwmon
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| D | amd,sbtsi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 Sideband interface Temperature Sensor Interface (SB-TSI) compliant
9 AMD SoC temperature device
12 - Kun Yi <kunyi@google.com>
13 - Supreeth Venkatesh <supreeth.venkatesh@amd.com>
16 SB Temperature Sensor Interface (SB-TSI) is an SMBus compatible
17 interface that reports AMD SoC's Ttcl (normalized temperature),
18 and resembles a typical 8-pin remote temperature sensor's I2C interface
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| /Documentation/devicetree/bindings/gpio/ |
| D | 8xxx_gpio.txt | 3 This is for the non-QE/CPM/GUTs GPIO controllers as found on
6 Every GPIO controller node must have #gpio-cells property defined,
7 this information will be used to translate gpio-specifiers.
11 The GPIO module usually is connected to the SoC's internal interrupt
12 controller, see bindings/interrupt-controller/interrupts.txt (the
14 module's interrupt.
17 the SoC's internal interrupt controller). See the interrupt controller
18 nodes section in bindings/interrupt-controller/interrupts.txt for
22 - compatible: "fsl,<chip>-gpio" followed by "fsl,mpc8349-gpio"
23 for 83xx, "fsl,mpc8572-gpio" for 85xx, or
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| /Documentation/devicetree/bindings/soc/renesas/ |
| D | renesas-soc.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/soc/renesas/renesas-soc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas SoC compatibles naming convention
10 - Geert Uytterhoeven <geert+renesas@glider.be>
11 - Niklas Söderlund <niklas.soderlund@ragnatech.se>
14 Guidelines for new compatibles for SoC blocks/components.
16 renesas,SoC-IP
19 renesas,r8a77965-csi2
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| /Documentation/devicetree/bindings/clock/st/ |
| D | st,quadfs.txt | 2 certain STMicroelectronics consumer electronics SoC devices.
10 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
13 - compatible : shall be:
15 "st,quadfs-d0"
16 "st,quadfs-d2"
17 "st,quadfs-d3"
18 "st,quadfs-pll"
21 - #clock-cells : from common clock binding; shall be set to 1.
23 - reg : A Base address and length of the register set.
25 - clocks : from common clock binding
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| /Documentation/devicetree/bindings/watchdog/ |
| D | aspeed,ast2400-wdt.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/aspeed,ast2400-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Jeffery <andrew@codeconstruct.com.au>
15 - aspeed,ast2400-wdt
16 - aspeed,ast2500-wdt
17 - aspeed,ast2600-wdt
29 aspeed,reset-type:
32 - cpu
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| /Documentation/devicetree/bindings/reset/ |
| D | delta,tn48m-reset.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/delta,tn48m-reset.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Robert Marko <robert.marko@sartura.hr>
13 This module is part of the Delta TN48M multi-function device. For more
14 details see ../mfd/delta,tn48m-cpld.yaml.
17 * 88F7040 SoC
18 * 88F6820 SoC
19 * 98DX3265 switch MAC-s
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| /Documentation/devicetree/bindings/sound/ |
| D | armada-370db-audio.txt | 9 * compatible: must be "marvell,a370db-audio"
11 * marvell,audio-controller: a phandle that points to the audio
12 controller of the Armada 370 SoC.
14 * marvell,audio-codec: a set of three phandles that points to:
16 1/ the analog audio codec connected to the Armada 370 SoC
17 2/ the S/PDIF transceiver
18 3/ the S/PDIF receiver
23 compatible = "marvell,a370db-audio";
24 marvell,audio-controller = <&audio_controller>;
25 marvell,audio-codec = <&audio_codec &spdif_out &spdif_in>;
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| /Documentation/devicetree/bindings/edac/ |
| D | apm-xgene-edac.txt | 1 * APM X-Gene SoC EDAC node
3 EDAC node is defined to describe on-chip error detection and correction.
6 memory controller - Memory controller
7 PMD (L1/L2) - Processor module unit (PMD) L1/L2 cache
8 L3 - L3 cache controller
9 SoC - SoC IP's such as Ethernet, SATA, and etc
14 - compatible : Shall be "apm,xgene-edac".
15 - regmap-csw : Regmap of the CPU switch fabric (CSW) resource.
16 - regmap-mcba : Regmap of the MCB-A (memory bridge) resource.
17 - regmap-mcbb : Regmap of the MCB-B (memory bridge) resource.
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| /Documentation/devicetree/bindings/regulator/ |
| D | nvidia,tegra-regulators-coupling.txt | 4 NVIDIA Tegra SoC's have a mandatory voltage-coupling between regulators.
9 ------------------------
11 On Tegra20 SoC's there are 3 coupled regulators: CORE, RTC and CPU.
16 ------------------------
18 On Tegra30 SoC's there are 2 coupled regulators: CORE and CPU. The CORE
24 - nvidia,tegra-core-regulator: Boolean property that designates regulator
26 - nvidia,tegra-rtc-regulator: Boolean property that designates regulator
28 - nvidia,tegra-cpu-regulator: Boolean property that designates regulator
36 regulator-name = "vdd_core";
37 regulator-min-microvolt = <950000>;
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| /Documentation/devicetree/bindings/input/ |
| D | omap-keypad.txt | 1 * TI's Keypad Controller device tree bindings
3 TI's Keypad controller is used to interface a SoC with a matrix-type
6 The keypad controller can sense a key-press and key-release and report the
9 This binding is based on the matrix-keymap binding with the following
12 keypad,num-rows and keypad,num-columns are required.
14 Required SoC Specific Properties:
15 - compatible: should be one of the following
16 - "ti,omap4-keypad": For controllers compatible with omap4 keypad
20 - linux,keypad-no-autorepeat: do no enable autorepeat feature.
24 compatible = "ti,omap4-keypad";
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| D | twl4030-keypad.txt | 1 * TWL4030's Keypad Controller device tree bindings
3 TWL4030's Keypad controller is used to interface a SoC with a matrix-type
6 The keypad controller can sense a key-press and key-release and report the
9 This binding is based on the matrix-keymap binding with the following
12 * keypad,num-rows and keypad,num-columns are required.
14 Required SoC Specific Properties:
15 - compatible: should be one of the following
16 - "ti,twl4030-keypad": For controllers compatible with twl4030 keypad
18 - interrupt: should be one of the following
19 - <1>: For controllers compatible with twl4030 keypad controller.
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| /Documentation/admin-guide/perf/ |
| D | xgene-pmu.rst | 2 APM X-Gene SoC Performance Monitoring Unit (PMU)
5 X-Gene SoC PMU consists of various independent system device PMUs such as
6 L3 cache(s), I/O bridge(s), memory controller bridge(s) and memory
7 controller(s). These PMU devices are loosely architected to follow the
12 -----------------
14 The xgene-pmu driver registers several perf PMU drivers. Each of the perf
21 can be used with perf tool. For example, "l3c0/bank-fifo-full/" is an
24 Most of the SoC PMU has a specific list of agent ID used for monitoring
32 each PMU, please refer to APM X-Gene User Manual.
39 / # perf list | grep -e l3c -e iob -e mcb -e mc
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| /Documentation/devicetree/bindings/arm/ |
| D | amazon,al.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Amazon's Annapurna Labs Alpine Platform
10 - Hanna Hawa <hhhawa@amazon.com>
11 - Talel Shenhar <talel@amazon.com>, <talelshenhar@gmail.com>
12 - Ronen Krupnik <ronenk@amazon.com>
17 - description: Boards with Alpine V1 SoC
19 - const: al,alpine
21 - description: Boards with Alpine V2 SoC
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| /Documentation/devicetree/bindings/arm/keystone/ |
| D | ti,sci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI-SCI controller
10 - Nishanth Menon <nm@ti.com>
13 Texas Instrument's processors including those belonging to Keystone generation
15 management of the System on Chip (SoC) system. These include various system
18 An example of such an SoC is K2G, which contains the system control hardware
23 See https://software-dl.ti.com/tisci/esd/latest/index.html for protocol definition.
25 The TI-SCI node describes the Texas Instrument's System Controller entity node.
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