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/Documentation/devicetree/bindings/reset/
Damlogic,meson-reset.yaml16 - amlogic,meson8b-reset # Reset Controller on Meson8b and compatible SoCs
17 - amlogic,meson-gxbb-reset # Reset Controller on GXBB and compatible SoCs
18 - amlogic,meson-axg-reset # Reset Controller on AXG and compatible SoCs
19 - amlogic,meson-a1-reset # Reset Controller on A1 and compatible SoCs
20 - amlogic,meson-s4-reset # Reset Controller on S4 and compatible SoCs
21 - amlogic,c3-reset # Reset Controller on C3 and compatible SoCs
Dqcom,aoss-reset.yaml14 subsystem) for Qualcomm Technologies Inc SoCs.
19 - description: on SC7180 SoCs the following compatibles must be specified
24 - description: on SC7280 SoCs the following compatibles must be specified
29 - description: on SDM845 SoCs the following compatibles must be specified
Dqcom,pdc-global.yaml14 Controller) block for Qualcomm Technologies Inc SoCs.
19 - description: on SC7180 SoCs the following compatibles must be specified
24 - description: on SC7280 SoCs the following compatibles must be specified
28 - description: on SDM845 SoCs the following compatibles must be specified
/Documentation/arch/arm/
Dsunxi.rst2 ARM Allwinner SoCs
5 This document lists all the ARM Allwinner SoCs that are currently
7 provide links to documentation and/or datasheet for these SoCs.
15 * ARM926 based SoCs
20 * ARM Cortex-A8 based SoCs
47 * Single ARM Cortex-A7 based SoCs
54 * Dual ARM Cortex-A7 based SoCs
71 * Quad ARM Cortex-A7 based SoCs
123 * Quad ARM Cortex-A15, Quad ARM Cortex-A7 based SoCs
130 * Octa ARM Cortex-A7 based SoCs
[all …]
Dmicrochip.rst2 ARM Microchip SoCs (aka AT91)
8 This document gives useful information about the ARM Microchip SoCs that are
18 AT91 SoCs
31 * ARM 926 based SoCs
101 * ARM Cortex-A5 based SoCs
114 * ARM Cortex-A5 + NEON based SoCs
140 * ARM Cortex-A7 based SoCs
205 Device Tree for AT91 SoCs and boards
207 All AT91 SoCs are converted to Device Tree. Since Linux 3.19, these products
211 Device Tree files and Device Tree bindings that apply to AT91 SoCs and boards are
[all …]
/Documentation/devicetree/bindings/regulator/
Dpbias-regulator.txt1 PBIAS internal regulator for SD card dual voltage i/o pads on OMAP SoCs.
14 pbias_mmc_omap2430 for OMAP2430, OMAP3 SoCs
15 pbias_sim_omap3 for OMAP3 SoCs
16 pbias_mmc_omap4 for OMAP4 SoCs
/Documentation/devicetree/bindings/interrupt-controller/
Dti,pruss-intc.yaml28 The K3 family of SoCs can handle 160 input events that can be mapped to 20
44 Use "ti,pruss-intc" for OMAP-L13x/AM18x/DA850 SoCs,
45 AM335x family of SoCs,
46 AM437x family of SoCs,
47 AM57xx family of SoCs
48 66AK2G family of SoCs
49 Use "ti,icssg-intc" for K3 AM65x, J721E and AM64x family of SoCs
93 Eg: - AM437x and 66AK2G SoCs do not have "host_intr5" interrupt
95 - AM65x and J721E SoCs have "host_intr5", "host_intr6" and
98 - AM64x SoCs have all the 8 host interrupts connected to various
/Documentation/arch/mips/
Dingenic-tcu.rst4 Ingenic JZ47xx SoCs Timer/Counter Unit hardware
7 The Timer/Counter Unit (TCU) in Ingenic JZ47xx SoCs is a multi-function
11 - JZ4725B, JZ4750, JZ4755 only have six TCU channels. The other SoCs all
35 - On the oldest SoCs (up to JZ4740), all of the eight channels operate in
38 - On newest SoCs (JZ4750 and above), channels 1-2 operate as TCU2, the
44 - on older SoCs (JZ4740 and below), channel 0 and channel 1 have their
48 - on newer SoCs (JZ4750 and above), channel 5 has its own interrupt;
/Documentation/devicetree/bindings/hwlock/
Dti,omap-hwspinlock.yaml7 title: TI HwSpinlock for OMAP and K3 based SoCs
15 - ti,omap4-hwspinlock # for OMAP44xx, OMAP54xx, AM33xx, AM43xx, DRA7xx SoCs
16 - ti,am64-hwspinlock # for K3 AM64x SoCs
17 - ti,am654-hwspinlock # for K3 AM65x, J721E and J7200 SoCs
/Documentation/devicetree/bindings/spi/
Dspi-orion.txt5 - "marvell,orion-spi" for the Orion, mv78x00, Kirkwood and Dove SoCs
6 - "marvell,armada-370-spi", for the Armada 370 SoCs
7 - "marvell,armada-375-spi", for the Armada 375 SoCs
8 - "marvell,armada-380-spi", for the Armada 38x SoCs
9 - "marvell,armada-390-spi", for the Armada 39x SoCs
10 - "marvell,armada-xp-spi", for the Armada XP SoCs
13 the SPI direct access mode that some of the Marvell SoCs support
/Documentation/devicetree/bindings/remoteproc/
Dti,keystone-rproc.txt4 The TI Keystone 2 family of SoCs usually have one or more (upto 8) TI DSP Core
11 Keystone 2 SoCs is usually a TMS320C66x CorePac processor.
26 "ti,k2hk-dsp" for DSPs on Keystone 2 66AK2H/K SoCs
27 "ti,k2l-dsp" for DSPs on Keystone 2 66AK2L SoCs
28 "ti,k2e-dsp" for DSPs on Keystone 2 66AK2E SoCs
29 "ti,k2g-dsp" for DSPs on Keystone 2 66AK2G SoCs
50 for 66AK2HK/66AK2L/66AK2E SoCs or,
52 for 66AK2G SoCs
74 SoCs only:
80 The following are mandatory properties for Keystone 2 66AK2G SoCs only:
/Documentation/devicetree/bindings/i2c/
Di2c-owl.yaml13 This I2C controller is found in the Actions Semi Owl SoCs:
22 - actions,s500-i2c # Actions Semi S500 compatible SoCs
23 - actions,s700-i2c # Actions Semi S700 compatible SoCs
24 - actions,s900-i2c # Actions Semi S900 compatible SoCs
Damlogic,meson6-i2c.yaml20 - amlogic,meson6-i2c # Meson6, Meson8 and compatible SoCs
21 - amlogic,meson-gxbb-i2c # GXBB and compatible SoCs
22 - amlogic,meson-axg-i2c # AXG and compatible SoCs
/Documentation/devicetree/bindings/phy/
Drealtek,usb3phy.yaml8 title: Realtek DHC SoCs USB 3.0 PHY
14 Realtek USB 3.0 PHY support the digital home center (DHC) RTD series SoCs.
15 The USB 3.0 PHY driver is designed to support the XHCI controller. The SoCs
19 RTD1295/RTD1619 SoCs USB
29 RTD1319/RTD1619b SoCs USB
37 RTD1319d SoCs USB
Drealtek,usb2phy.yaml8 title: Realtek DHC SoCs USB 2.0 PHY
14 Realtek USB 2.0 PHY support the digital home center (DHC) RTD series SoCs.
15 The USB 2.0 PHY driver is designed to support the XHCI controller. The SoCs
19 RTD1295/RTD1619 SoCs USB
29 RTD1395 SoCs USB
37 RTD1319/RTD1619b SoCs USB
45 RTD1319d SoCs USB
53 RTD1312c/RTD1315e SoCs USB
/Documentation/devicetree/bindings/clock/
Dmarvell,berlin.txt9 (BG2, BG2CD, BG2Q) SoCs share the same IP for PLLs and clocks, with some
18 "refclk" for the SoCs oscillator input on all SoCs,
Dmediatek,mtmips-sysc.yaml7 title: MTMIPS SoCs System Controller
13 MediaTek MIPS and Ralink SoCs provides a system controller to allow
18 These SoCs have an XTAL from where the cpu clock is
/Documentation/devicetree/bindings/mailbox/
Dti,omap-mailbox.yaml24 into the SoC (excluding the SoCs that have an Interrupt Crossbar or an
32 registers. All the current OMAP SoCs except for the newest DRA7xx SoC has a
37 K3 AM65x, J721E and J7200 SoCs has each of these instances form a cluster and
41 output lines of an Interrupt Router. The AM64x SoCS also uses a single IP
110 communicate with WkupM3 remote processor on AM33xx/AM43xx SoCs.
119 - ti,omap2-mailbox # for OMAP2420, OMAP2430 SoCs
120 - ti,omap3-mailbox # for OMAP3430, OMAP3630 SoCs
121 - ti,omap4-mailbox # for OMAP44xx, OMAP54xx, AM33xx, AM43xx and DRA7xx SoCs
122 - ti,am654-mailbox # for K3 AM65x, J721E and J7200 SoCs
123 - ti,am64-mailbox # for K3 AM64x SoCs
[all …]
/Documentation/devicetree/bindings/soc/amlogic/
Damlogic,canvas.yaml19 Many IPs within Amlogic SoCs rely on canvas indexes to read/write pixel data
23 Amlogic SoCs have 256 canvas.
34 - const: amlogic,canvas # GXBB and newer SoCs
/Documentation/driver-api/phy/
Dsamsung-usb2.rst8 The architecture of the USB 2.0 PHY module in Samsung SoCs is similar
9 among many SoCs. In spite of the similarities it proved difficult to
28 struct of_device_id definitions for particular SoCs.
33 structures that describe particular SoCs.
35 3. Supporting SoCs
119 include support for selected SoCs in the compiled driver. The Kconfig
/Documentation/ABI/testing/
Dsysfs-devices-soc19 Read-only attribute common to all SoCs. Contains the SoC machine
26 Read-only attribute common to all SoCs. Contains SoC family name
57 Read-only attribute supported by most SoCs. Contains the SoC's
64 Read-only attribute supported by most SoCs. In the case of
77 Read-only attribute supported by most SoCs. Contains the SoC's
/Documentation/devicetree/bindings/arm/
Dsyna.txt5 berlin SoCs are now Synaptics' SoCs now.
50 Marvell Berlin SoCs have a chip control register set providing several
66 Marvell Berlin SoCs have a system control register set providing several
/Documentation/devicetree/bindings/usb/
Dgeneric-xhci.yaml17 - description: Armada 37xx/375/38x/8k SoCs
25 - description: Broadcom SoCs with power domains
30 - description: Broadcom STB SoCs with xHCI
/Documentation/devicetree/bindings/net/
Dcdns,macb.yaml37 - cdns,at91sam9260-macb # Atmel at91sam9 SoCs
44 - atmel,sama5d3-macb # 10/100Mbit IP on Atmel sama5d3 SoCs
46 - cdns,at91sam9260-macb # Atmel at91sam9 SoCs.
50 - atmel,sama5d29-gem # GEM XL IP (10/100) on Atmel sama5d29 SoCs
51 - atmel,sama5d2-gem # GEM IP (10/100) on Atmel sama5d2 SoCs
52 - atmel,sama5d3-gem # Gigabit IP on Atmel sama5d3 SoCs
53 - atmel,sama5d4-gem # GEM IP (10/100) on Atmel sama5d4 SoCs
/Documentation/devicetree/bindings/serial/
Damlogic,meson-uart.yaml15 of SoCs, and can be present either in the "Always-On" power domain or the
38 - description: Always-on power domain UART controller on G12A SoCs
51 - description: Everything-Else power domain UART controller on G12A SoCs
55 - description: UART controller on S4 compatible SoCs

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