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/Documentation/devicetree/bindings/arm/
Darm,coresight-dummy-source.yaml4 $id: http://devicetree.org/schemas/arm/arm,coresight-dummy-source.yaml#
7 title: ARM Coresight Dummy source component
14 through the intermediate links connecting the source to the currently selected
17 The Coresight dummy source component is for the specific coresight source
19 there would be Coresight source trace components on sub-processor which
21 is needed to register them as Coresight source devices, so that paths can be
23 source devices, such as enabling and disabling them. It also provides the
24 Coresight dummy source paths for debugging.
26 The primary use case of the coresight dummy source is to build path in kernel
27 side for dummy source component.
[all …]
/Documentation/devicetree/bindings/clock/
Dqcom,sdx75-gcc.yaml25 - description: Board XO source
26 - description: Sleep clock source
27 - description: EMAC0 sgmiiphy mac rclk source
28 - description: EMAC0 sgmiiphy mac tclk source
29 - description: EMAC0 sgmiiphy rclk source
30 - description: EMAC0 sgmiiphy tclk source
31 - description: EMAC1 sgmiiphy mac rclk source
32 - description: EMAC1 sgmiiphy mac tclk source
33 - description: EMAC1 sgmiiphy rclk source
34 - description: EMAC1 sgmiiphy tclk source
[all …]
Dqcom,gcc-sm8350.yaml24 - description: Board XO source
25 - description: Sleep clock source
26 - description: PCIE 0 Pipe clock source (Optional clock)
27 - description: PCIE 1 Pipe clock source (Optional clock)
28 - description: UFS card Rx symbol 0 clock source (Optional clock)
29 - description: UFS card Rx symbol 1 clock source (Optional clock)
30 - description: UFS card Tx symbol 0 clock source (Optional clock)
31 - description: UFS phy Rx symbol 0 clock source (Optional clock)
32 - description: UFS phy Rx symbol 1 clock source (Optional clock)
33 - description: UFS phy Tx symbol 0 clock source (Optional clock)
[all …]
Dqcom,sm8650-gcc.yaml24 - description: Board XO source
25 - description: Board Always On XO source
26 - description: Sleep clock source
27 - description: PCIE 0 Pipe clock source
28 - description: PCIE 1 Pipe clock source
29 - description: PCIE 1 Phy Auxiliary clock source
30 - description: UFS Phy Rx symbol 0 clock source
31 - description: UFS Phy Rx symbol 1 clock source
32 - description: UFS Phy Tx symbol 0 clock source
33 - description: USB3 Phy wrapper pipe clock source
Dsilabs,si5351.yaml53 silabs,pll-source:
56 A list of cell pairs containing a PLL index and its source. Allows to
57 overwrite clock source of the internal PLLs.
62 - description: PLL source, XTAL (0) or CLKIN (1, Si5351C only).
98 silabs,clock-source:
101 Source clock of the this output's divider stage.
114 silabs,multisynth-source:
118 Source PLL A (0) or B (1) for the corresponding multisynth divider.
123 The frequency of the source PLL is allowed to be changed by the
128 description: Reset the source PLL when enabling this clock output.
[all …]
Dqcom,ipq5018-gcc.yaml26 - description: Board XO source
27 - description: Sleep clock source
28 - description: PCIE20 PHY0 pipe clock source
29 - description: PCIE20 PHY1 pipe clock source
30 - description: USB3 PHY pipe clock source
31 - description: GEPHY RX clock source
32 - description: GEPHY TX clock source
33 - description: UNIPHY RX clock source
34 - description: UNIPHY TX clk source
Dqcom,sm8550-gcc.yaml24 - description: Board XO source
25 - description: Sleep clock source
26 - description: PCIE 0 Pipe clock source
27 - description: PCIE 1 Pipe clock source
28 - description: PCIE 1 Phy Auxiliary clock source
29 - description: UFS Phy Rx symbol 0 clock source
30 - description: UFS Phy Rx symbol 1 clock source
31 - description: UFS Phy Tx symbol 0 clock source
32 - description: USB3 Phy wrapper pipe clock source
Dqcom,ipq9574-gcc.yaml27 - description: Board XO source
28 - description: Sleep clock source
29 - description: Bias PLL ubi clock source
30 - description: PCIE30 PHY0 pipe clock source
31 - description: PCIE30 PHY1 pipe clock source
32 - description: PCIE30 PHY2 pipe clock source
33 - description: PCIE30 PHY3 pipe clock source
34 - description: USB3 PHY pipe clock source
Dqcom,gcc-sm8450.yaml24 - description: Board XO source
25 - description: Sleep clock source
26 - description: PCIE 0 Pipe clock source (Optional clock)
27 - description: PCIE 1 Pipe clock source (Optional clock)
28 - description: PCIE 1 Phy Auxiliary clock source (Optional clock)
29 - description: UFS Phy Rx symbol 0 clock source (Optional clock)
30 - description: UFS Phy Rx symbol 1 clock source (Optional clock)
31 - description: UFS Phy Tx symbol 0 clock source (Optional clock)
32 - description: USB3 Phy wrapper pipe clock source (Optional clock)
Dqcom,gcc-sc7280.yaml24 - description: Board XO source
25 - description: Board active XO source
26 - description: Sleep clock source
27 - description: PCIE-0 pipe clock source
28 - description: PCIE-1 pipe clock source
29 - description: USF phy rx symbol 0 clock source
30 - description: USF phy rx symbol 1 clock source
31 - description: USF phy tx symbol 0 clock source
32 - description: USB30 phy wrapper pipe clock source
Dqcom,gcc-sdm845.yaml51 - description: Board XO source
52 - description: Board active XO source
53 - description: Sleep clock source
69 - description: Board XO source
70 - description: Board active XO source
71 - description: Sleep clock source
72 - description: PCIE 0 Pipe clock source
73 - description: PCIE 1 Pipe clock source
Dqcom,qdu1000-ecpricc.yaml29 - description: Board XO source
30 - description: GPLL0 source from GCC
31 - description: GPLL1 source from GCC
32 - description: GPLL2 source from GCC
33 - description: GPLL3 source from GCC
34 - description: GPLL4 source from GCC
35 - description: GPLL5 source from GCC
Dqcom,sm4450-gcc.yaml25 - description: Board XO source
26 - description: Sleep clock source
27 - description: UFS Phy Rx symbol 0 clock source
28 - description: UFS Phy Rx symbol 1 clock source
29 - description: UFS Phy Tx symbol 0 clock source
30 - description: USB3 Phy wrapper pipe clock source
/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/
Ducc.txt22 - rx-clock-name: the UCC receive clock source
23 "none": clock source is disabled
24 "brg1" through "brg16": clock source is BRG1-BRG16, respectively
25 "clk1" through "clk24": clock source is CLK1-CLK24, respectively
26 - tx-clock-name: the UCC transmit clock source
27 "none": clock source is disabled
28 "brg1" through "brg16": clock source is BRG1-BRG16, respectively
29 "clk1" through "clk24": clock source is CLK1-CLK24, respectively
35 - rx-clock : represents the UCC receive clock source.
36 0x00 : clock source is disabled;
[all …]
Dusb.txt9 - fsl,fullspeed-clock : specifies the full speed USB clock source:
10 "none": clock source is disabled
11 "brg1" through "brg16": clock source is BRG1-BRG16, respectively
12 "clk1" through "clk24": clock source is CLK1-CLK24, respectively
13 - fsl,lowspeed-clock : specifies the low speed USB clock source:
14 "none": clock source is disabled
15 "brg1" through "brg16": clock source is BRG1-BRG16, respectively
16 "clk1" through "clk24": clock source is CLK1-CLK24, respectively
/Documentation/ABI/testing/
Dsysfs-class-wakeup12 This file contains the name of the wakeup source.
18 This file contains the number of times the wakeup source was
26 associated with the wakeup source.
32 This file contains the number of times the wakeup source might
39 This file contains the number of times the wakeup source's
46 This file contains the amount of time the wakeup source has
48 source is not active, this file contains '0'.
54 This file contains the total amount of time this wakeup source
62 source has been continuously active, in milliseconds.
69 source was touched last time, in milliseconds.
[all …]
Dsysfs-pps14 PPS source into the system. Each directory will
15 contain files to manage and control its PPS source.
22 and the assert sequence number of the X-th source in the form:
26 If the source has no assert events the content of this file
34 and the clear sequence number of the X-th source in the form:
38 If the source has no clear events the content of this file
46 mode of the X-th source in hexadecimal encoding.
63 X-th source.
70 the device connected with the X-th source.
72 If the source is not connected with any device the content
/Documentation/driver-api/
Dpps.rst27 PPS means "pulse per second" and a PPS source is just a device which
31 A PPS source can be connected to a serial port (usually to the Data
38 GPS receiver as PPS source, to obtain a wallclock-time with
52 This implies that the source has a /dev/... entry. This assumption is
60 The problem can be simply solved if you consider that a PPS source is
61 not always connected with a GPS data source.
63 So your programs should check if the GPS data source (the serial port
64 for instance) is a PPS source too, and if not they should provide the
65 possibility to open another device as PPS source.
92 To register a PPS source into the kernel you should define a struct
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/Documentation/devicetree/bindings/pinctrl/
Dpinctrl-max77620.txt46 - maxim,active-fps-source: FPS source for the GPIOs to get
50 FPS source is FPS0.
52 FPS source is FPS1
54 FPS source is FPS2
68 This is applicable if FPS source is
75 This is applicable if FPS source is
78 - maxim,suspend-fps-source: This is same as property
79 "maxim,active-fps-source" but value
89 FPS source is selected as FPS0, FPS1 or
97 FPS source is selected as FPS0, FPS1 or
[all …]
/Documentation/devicetree/bindings/net/can/
Dmpc5xxx-mscan.txt10 also specify which clock source shall be used for the controller:
12 - fsl,mscan-clock-source : a string describing the clock source. Valid values
21 also specify which clock source and divider shall be used for the controller:
23 - fsl,mscan-clock-source : a string describing the clock source. Valid values
28 clock source and frequency based on the system
51 fsl,mscan-clock-source = "ref";
/Documentation/admin-guide/device-mapper/
Ddm-clone.rst11 existing, read-only source device into a writable destination device: It
18 and the copy of the source device to the destination device happens in the
37 the same region of the source device, i.e., copying the region from the
38 source to the destination device.
52 1. A source device - the read-only device that gets cloned and source of the
56 clone of the source device.
63 source device.
68 dm-clone divides the source and destination devices in fixed sized regions.
70 the source to the destination device.
80 A read to a not yet hydrated region is serviced directly from the source device.
[all …]
/Documentation/devicetree/bindings/leds/
Dtrigger-source.yaml4 $id: http://devicetree.org/schemas/leds/trigger-source.yaml#
7 title: Trigger source providers
14 Each trigger source provider should be represented by a device tree node. It
18 '#trigger-source-cells':
20 Number of cells in a source trigger. Typically 0 for nodes of simple
/Documentation/timers/
Dtimekeeping.rst10 If you grep through the kernel source you will find a number of architecture-
15 To provide timekeeping for your platform, the clock source provides
19 provide an accurate delay source using hardware counters.
25 The purpose of the clock source is to provide a timeline for the system that
27 a Linux system will eventually read the clock source to determine exactly
30 Typically the clock source is a monotonic, atomic counter which will provide
35 The clock source shall have as high resolution as possible, and the frequency
46 When the wall-clock accuracy of the clock source isn't satisfactory, there
50 the clock source, which provides the fundamental timeline for the system.
51 These measures does not affect the clock source per se, they only adapt the
[all …]
/Documentation/devicetree/bindings/sound/
Dmediatek,mt2701-audio.yaml41 - description: i2s0 source selection
42 - description: i2s1 source selection
43 - description: i2s2 source selection
44 - description: i2s3 source selection
45 - description: i2s0 source divider
46 - description: i2s1 source divider
47 - description: i2s2 source divider
48 - description: i2s3 source divider
/Documentation/devicetree/bindings/interrupt-controller/
Darm,vic.yaml45 represents single interrupt source, starting from source 0 at
46 LSb and ending at source 31 at MSb. A bit that is set means
47 that the source is wired and clear means otherwise. If unspecified,
54 as wake up source for the system. Order of bits is the same as for
55 valid-mask property. A set bit means that this interrupt source
56 can be configured as a wake up source for the system. If unspecied,

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