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/Documentation/devicetree/bindings/remoteproc/
Dti,omap-remoteproc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,omap-remoteproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
13 The OMAP family of SoCs usually have one or more slave processor sub-systems
14 that are used to offload some of the processor-intensive tasks, or to manage
15 other hardware accelerators, for achieving various system level goals.
17 The processor cores in the sub-system are usually behind an IOMMU, and may
18 contain additional sub-modules like Internal RAM and/or ROMs, L1 and/or L2
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Dti,davinci-rproc.txt4 The TI Davinci family of SoCs usually contains a TI DSP Core sub-system that
5 is used to offload some of the processor-intensive tasks or algorithms, for
6 achieving various system level goals.
8 The processor cores in the sub-system usually contain additional sub-modules
15 Each DSP Core sub-system is represented as a single DT node.
18 --------------------
21 - compatible: Should be one of the following,
22 "ti,da850-dsp" for DSPs on OMAP-L138 SoCs
24 - reg: Should contain an entry for each value in 'reg-names'.
27 the parent node's '#address-cells' and '#size-cells' values.
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Dti,k3-dsp-rproc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,k3-dsp-rproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
13 The TI K3 family of SoCs usually have one or more TI DSP Core sub-systems
14 that are used to offload some of the processor-intensive tasks or algorithms,
15 for achieving various system level goals.
17 These processor sub-systems usually contain additional sub-modules like
23 Each DSP Core sub-system is represented as a single DT node. Each node has a
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Dqcom,q6v5.txt6 - compatible:
10 "qcom,ipq8074-wcss-pil"
11 "qcom,qcs404-wcss-pil"
13 - reg:
15 Value type: <prop-encoded-array>
19 - reg-names:
24 - interrupts-extended:
26 Value type: <prop-encoded-array>
27 Definition: reference to the interrupts that match interrupt-names
29 - interrupt-names:
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/Documentation/devicetree/bindings/rng/
Dsamsung,exynos5250-trng.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/rng/samsung,exynos5250-trng.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Łukasz Stelmach <l.stelmach@samsung.com>
16 - samsung,exynos5250-trng
17 - samsung,exynos850-trng
23 clock-names:
31 - compatible
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/Documentation/admin-guide/perf/
Dalibaba_pmu.rst2 Alibaba's T-Head SoC Uncore Performance Monitoring Unit (PMU)
5 The Yitian 710, custom-built by Alibaba Group's chip development business,
6 T-Head, implements uncore PMU for performance and functional debugging to
7 facilitate system maintenance.
9 DDR Sub-System Driveway (DRW) PMU Driver
13 is independent of others to service system memory requests. And one DDR5
14 channel is split into two independent sub-channels. The DDR Sub-System Driveway
15 implements separate PMUs for each sub-channel to monitor various performance
20 sub-channels of the same channel in die 0. And the PMU device of die 1 is
23 Each sub-channel has 36 PMU counters in total, which is classified into
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/Documentation/devicetree/bindings/regulator/
Dmax8907.txt4 - compatible: "maxim,max8907"
5 - reg: I2C slave address
6 - interrupts: The interrupt output of the controller
7 - mbatt-supply: The input supply for MBATT, BBAT, SDBY, VRTC.
8 - in-v1-supply: The input supply for SD1.
9 - in-v2-supply: The input supply for SD2.
10 - in-v3-supply: The input supply for SD3.
11 - in1-supply: The input supply for LDO1.
13 - in20-supply: The input supply for LDO20.
14 - regulators: A node that houses a sub-node for each regulator within the
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Dpalmas-pmic.txt11 - compatible : Should be from the list
12 ti,twl6035-pmic
13 ti,twl6036-pmic
14 ti,twl6037-pmic
15 ti,tps65913-pmic
16 ti,tps65914-pmic
17 ti,tps65917-pmic
18 ti,tps659038-pmic
20 ti,palmas-pmic
21 - interrupts : The interrupt number and the type which can be looked up here:
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Dtps6586x.txt4 - compatible: "ti,tps6586x"
5 - reg: I2C slave address
6 - interrupts: the interrupt outputs of the controller
7 - #gpio-cells: number of cells to describe a GPIO
8 - gpio-controller: mark the device as a GPIO controller
9 - regulators: A node that houses a sub-node for each regulator within the
10 device. Each sub-node is identified using the node's name (or the deprecated
11 regulator-compatible property if present), with valid values listed below.
12 The content of each sub-node is defined by the standard binding for
14 sys, sm[0-2], ldo[0-9] and ldo_rtc
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/Documentation/devicetree/bindings/clock/
Dthead,th1520-clk-ap.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/thead,th1520-clk-ap.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: T-HEAD TH1520 AP sub-system clock controller
10 The T-HEAD TH1520 AP sub-system clock controller configures the
14 …https://openbeagle.org/beaglev-ahead/beaglev-ahead/-/blob/main/docs/TH1520%20System%20User%20Manua…
17 - Jisheng Zhang <jszhang@kernel.org>
18 - Wei Fu <wefu@redhat.com>
19 - Drew Fustini <dfustini@tenstorrent.com>
[all …]
Dqcom,kpss-gcc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,kpss-gcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Krait Processor Sub-system (KPSS) Global Clock Controller (GCC)
10 - Christian Marangi <ansuelsmth@gmail.com>
13 Krait Processor Sub-system (KPSS) Global Clock Controller (GCC). Used
15 to the kpss-gcc registers.
20 - enum:
21 - qcom,kpss-gcc-ipq8064
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/Documentation/devicetree/bindings/net/wireless/
Dmarvell,sd8787.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Brian Norris <briannorris@chromium.org>
11 - Frank Li <Frank.Li@nxp.com>
16 connects the device to the system.
21 - marvell,sd8787
22 - marvell,sd8897
23 - marvell,sd8978
24 - marvell,sd8997
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/Documentation/devicetree/bindings/mfd/
Dmax77620.txt4 -------------------
5 - compatible: Must be one of
9 - reg: I2C device address.
12 -------------------
13 - interrupts: The interrupt on the parent the controller is
15 - interrupt-controller: Marks the device node as an interrupt controller.
16 - #interrupt-cells: is <2> and their usage is compliant to the 2 cells
17 variant of <../interrupt-controller/interrupts.txt>
19 are defined at dt-bindings/mfd/max77620.h.
21 - system-power-controller: Indicates that this PMIC is controlling the
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/Documentation/devicetree/bindings/arm/
Dsyna.txt3 According to https://www.synaptics.com/company/news/conexant-marvell
7 ---------------------------------------------------------------
18 "marvell,berlin2cd" for Marvell Armada 1500-mini (BG2CD, 88DE3005)
20 "marvell,berlin2q" for Marvell Armada 1500-pro (BG2Q, 88DE3114)
26 model = "Sony NSZ-GS7";
27 compatible = "sony,nsz-gs7", "marvell,berlin2", "marvell,berlin";
38 - compatible: should be "marvell,berlin-cpu-ctrl"
39 - reg: address and length of the register set
43 cpu-ctrl@f7dd0000 {
44 compatible = "marvell,berlin-cpu-ctrl";
[all …]
/Documentation/leds/
Dleds-class-flash.rst5 Some LED devices provide two modes - torch and flash. In the LED subsystem
6 those modes are supported by LED class (see Documentation/leds/leds-class.rst)
16 (see Documentation/ABI/testing/sysfs-class-led-flash)
18 - flash_brightness
19 - max_flash_brightness
20 - flash_timeout
21 - max_flash_timeout
22 - flash_strobe
23 - flash_fault
36 - dev:
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/Documentation/arch/arm/keystone/
Dknav-qmss.rst9 The QMSS (Queue Manager Sub System) found on Keystone SOCs is one of
10 the main hardware sub system which forms the backbone of the Keystone
11 multi-core Navigator. QMSS consist of queue managers, packed-data structure
15 management of the packet queues. Packets are queued/de-queued by writing or
29 Documentation/devicetree/bindings/soc/ti/keystone-navigator-qmss.txt
40 git://git.ti.com/keystone-rtos/qmss-lld.git
43 channels. This firmware is available under ti-keystone folder of
46 git://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git
49 ubifs file system and provide a sym link to k2_qmss_pdsp_acc48_k2_le_1_0_0_9.bin
50 in the file system and boot up the kernel. User would see
[all …]
/Documentation/devicetree/bindings/pinctrl/
Dberlin,pinctrl.txt1 * Pin-controller driver for the Marvell Berlin SoCs
3 Pin control registers are part of both chip controller and system
4 controller register sets. Pin controller nodes should be a sub-node of
5 either the chip controller or system controller node. The pins
9 A pin-controller node should contain subnodes representing the pin group
14 is called a 'function' in the pin-controller subsystem.
17 - compatible: should be one of:
18 "marvell,berlin2-soc-pinctrl",
19 "marvell,berlin2-system-pinctrl",
20 "marvell,berlin2cd-soc-pinctrl",
[all …]
Dimg,pistachio-pinctrl.txt5 interrupt controller, and pinmux + pinconf device. The system ("east") pin
8 each. The GPIO banks are represented as sub-nodes of the pad controller node.
10 Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and
11 ../interrupt-controller/interrupts.txt for generic information regarding
15 --------------------------------------------
16 - compatible: "img,pistachio-system-pinctrl".
17 - reg: Address range of the pinctrl registers.
19 Required properties for GPIO bank sub-nodes:
20 --------------------------------------------
21 - interrupts: Interrupt line for the GPIO bank.
[all …]
Dcanaan,k210-fpioa.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/canaan,k210-fpioa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Damien Le Moal <dlemoal@kernel.org>
16 a per-pin basis.
20 const: canaan,k210-fpioa
29 - description: Controller reference clock source
30 - description: APB interface clock source
32 clock-names:
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/Documentation/userspace-api/media/
Dglossary.rst1 .. SPDX-License-Identifier: GPL-2.0 OR GFDL-1.1-no-invariants-or-later
40 A character device node in the file system used to control and
58 **Field-programmable Gate Array**
63 See https://en.wikipedia.org/wiki/Field-programmable_gate_array.
72 together make a larger user-facing functional peripheral. For
80 **Inter-Integrated Circuit**
82 A multi-master, multi-slave, packet switched, single-ended,
84 like sub-device hardware components.
86 See http://www.nxp.com/docs/en/user-guide/UM10204.pdf.
120 - :term:`CEC API`;
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/Documentation/devicetree/bindings/pci/
Dsnps,dw-pcie-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
23 Interface - DBI. In accordance with the reference manual the register
24 configuration space belongs to the Configuration-Dependent Module (CDM)
25 and is split up into several sub-parts Standard PCIe configuration
26 space, Port Logic Registers (PL), Shadow Config-space Registers,
[all …]
/Documentation/userspace-api/media/v4l/
Dopen.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
22 the hardware, which may also expose device nodes, called V4L2 sub-devices.
24 When such V4L2 sub-devices are exposed, they allow controlling those
25 other hardware components - usually connected via a serial bus (like
26 I²C, SMBus or SPI). Depending on the bridge driver, those sub-devices
29 :ref:`V4L2 sub-devices <subdev>`.
32 :ref:`Media Controller <media_controller>` are called **MC-centric**
34 are called **video-node-centric**.
36 Userspace can check if a V4L2 hardware peripheral is MC-centric by
38 :ref:`device_caps field <device-capabilities>`.
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/Documentation/ABI/testing/
Dsysfs-bus-nfit10 (RO) Serial number of the NVDIMM (non-volatile dual in-line
44 (RO) Handle (i.e., instance number) for the SMBIOS (system
54 (RO) The flags in the NFIT memory device sub-structure indicate
74 mapped directly into system physical address space and / or a
80 only expect one code per-dimm as they will ignore
113 http://pmem.io/documents/NVDIMM_DSM_Interface-V1.6.pdf
114 https://github.com/HewlettPackard/hpe-nvm/blob/master/Documentation/
132 (RO) Sub-system vendor id of the NVDIMM non-volatile memory
141 (RO) Sub-system revision id of the NVDIMM non-volatile memory subsystem
142 controller, assigned by the non-volatile memory subsystem
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/Documentation/driver-api/media/
Dv4l2-subdev.rst1 .. SPDX-License-Identifier: GPL-2.0
3 V4L2 sub-devices
4 ----------------
6 Many drivers need to communicate with sub-devices. These devices can do all
8 encoding or decoding. For webcams common sub-devices are sensors and camera
12 driver with a consistent interface to these sub-devices the
13 :c:type:`v4l2_subdev` struct (v4l2-subdev.h) was created.
15 Each sub-device driver must have a :c:type:`v4l2_subdev` struct. This struct
16 can be stand-alone for simple sub-devices or it might be embedded in a larger
18 low-level device struct (e.g. ``i2c_client``) that contains the device data as
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/Documentation/admin-guide/media/
Dipu6-isys.rst1 .. SPDX-License-Identifier: GPL-2.0
6 Intel Image Processing Unit 6 (IPU6) Input System driver
9 Copyright |copy| 2023--2024 Intel Corporation
15 Input System (MIPI CSI2 receiver) drivers located under
26 Intel IPU6 is made up of two components - Input System (ISYS) and Processing
27 System (PSYS).
29 The Input System mainly works as MIPI CSI-2 receiver which receives and
32 There are 2 driver modules - intel-ipu6 and intel-ipu6-isys. intel-ipu6 is an
34 firmware authentication, DMA mapping and IPU-MMU (internal Memory mapping Unit)
36 sub-device interfaces. The IPU6 ISYS driver supports camera sensors connected
[all …]

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