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/Documentation/devicetree/bindings/interrupt-controller/
Driscv,cpu-intc.yaml16 The RISC-V supervisor ISA manual specifies three interrupt sources that are
20 time timer that is controlled via Supervisor Binary Interface (SBI) calls
25 All RISC-V systems that conform to the supervisor ISA specification are
50 The interrupt sources are defined by the RISC-V supervisor ISA manual,
52 supervisor mode:
53 - Source 1 is the supervisor software interrupt, which can be sent by
55 - Source 5 is the supervisor timer interrupt, which can be configured
57 - Source 9 is the supervisor external interrupt, which chains to all
Driscv,imsics.yaml18 for each privilege level (machine or supervisor). The configuration of
25 for each privilege level (machine or supervisor) which collectively describe
33 privilege level (machine or supervisor) encodes group index, HART index,
154 // Example 2 (Supervisor-level IMSIC files with two groups):
Dsifive,plic-1.0.0.yaml19 privilege modes per hart; machine mode and supervisor mode.
/Documentation/hwmon/
Dsl28cpld.rst21 supervisor. In the future there might be other flavours and additional
24 The fan supervisor has a 7 bit counter register and a counter period of 1
25 second. If the 7 bit counter overflows, the supervisor will automatically
Dpli1209bc.rst8 * Digital Supervisor PLI1209BC
22 The Vicor PLI1209BC is an isolated digital power system supervisor that provides
/Documentation/arch/x86/x86_64/
Dfred.rst20 establishes the full supervisor context and that event return
53 Full supervisor/user context
56 FRED event delivery atomically save and restore full supervisor/user
/Documentation/devicetree/bindings/riscv/
Dextensions.yaml126 The standard Smaia supervisor-level extension for the advanced
139 The standard Ssaia supervisor-level extension for the advanced
140 interrupt architecture for supervisor-mode-visible csr and
146 The standard Sscofpmf supervisor-level extension for count overflow
152 The standard Sstc supervisor-level extension for time compare as
158 The standard Svinval supervisor-level extension for fine-grained
164 The standard Svnapot supervisor-level extensions for napot
170 The standard Svpbmt supervisor-level extensions for page-based
176 The standard Svvptc supervisor-level extension for
/Documentation/arch/riscv/
Duabi.rst29 #. Standard supervisor-level extensions (starting with 'S') will be listed
30 after standard unprivileged extensions. If multiple supervisor-level
/Documentation/translations/zh_CN/core-api/
Derrseq.rst77 struct supervisor {
82 struct supervisor su;
/Documentation/devicetree/bindings/timer/
Driscv,timer.yaml13 RISC-V platforms always have a RISC-V timer device for the supervisor-mode
/Documentation/devicetree/bindings/hwmon/
Dlltc,ltc2978.yaml7 title: Octal Digital Power-supply monitor/supervisor/sequencer/margin controller.
/Documentation/virt/kvm/x86/
Dhypercalls.rst82 shared page that contains parts of supervisor visible register state.
83 The guest can map this shared page to access its supervisor register
/Documentation/core-api/
Derrseq.rst78 struct supervisor {
83 struct supervisor su;
Ddma-attributes.rst128 accesses to DMA buffers in both privileged "supervisor" and unprivileged
/Documentation/misc-devices/
Dmax6875.rst21 The Maxim MAX6875 is an EEPROM-programmable power-supply sequencer/supervisor.
/Documentation/arch/arm/nwfpe/
Dnetwinder-fpe.rst62 RFC/WFC are fully implemented. RFC/WFC are supervisor only instructions, and
64 from supervisor mode.
Dtodo.rst55 supervisor only instructions. If anyone has any ideas or comments I
/Documentation/userspace-api/
Dseccomp_filter.rst266 like O_CLOEXEC on the file descriptor in the notifying process. If the supervisor
270 notifying process it will be replaced. The supervisor can also add an FD, and
279 such that when a user notification is received by the supervisor, the notifying
/Documentation/translations/zh_CN/userspace-api/
Dseccomp_filter.rst218 O_CLOEXEC 等标志。如果监督者(supervisor)向文件描述符注入一个特定的数字,可以使用
/Documentation/devicetree/bindings/
Dtrivial-devices.yaml74 # CPU Supervisor with Nonvolatile Memory and Programmable I/O
403 # Vicor Corporation Digital Supervisor
/Documentation/driver-api/mei/
Dmei.rst45 In order to support virtualization or sandboxing a trusted supervisor
/Documentation/devicetree/bindings/perf/
Driscv,pmu.yaml13 The SBI PMU extension allows supervisor software to configure, start and
/Documentation/ABI/testing/
Dsysfs-class-firmware-attributes281 echo "supervisor password" > authentication/Admin/current_password
300 You cannot enable certificate authentication if a supervisor password
/Documentation/virt/kvm/
Dppc-pv.rst74 page that contains parts of supervisor visible register state. The guest can
/Documentation/arch/x86/
Dsva.rst86 This MSR is managed with the XSAVE feature set as "supervisor state" to

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