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/Documentation/devicetree/bindings/mfd/
Dqcom,tcsr.yaml4 $id: http://devicetree.org/schemas/mfd/qcom,tcsr.yaml#
20 - qcom,msm8976-tcsr
21 - qcom,msm8998-tcsr
22 - qcom,qcm2290-tcsr
23 - qcom,qcs404-tcsr
24 - qcom,sa8775p-tcsr
25 - qcom,sc7180-tcsr
26 - qcom,sc7280-tcsr
27 - qcom,sc8280xp-tcsr
28 - qcom,sdm630-tcsr
[all …]
/Documentation/devicetree/bindings/hwlock/
Dqcom-hwspinlock.yaml21 - qcom,tcsr-mutex
24 - qcom,apq8084-tcsr-mutex
25 - qcom,ipq6018-tcsr-mutex
26 - qcom,msm8226-tcsr-mutex
27 - qcom,msm8994-tcsr-mutex
28 - const: qcom,tcsr-mutex
31 - qcom,msm8974-tcsr-mutex
32 - const: qcom,tcsr-mutex
51 compatible = "qcom,tcsr-mutex";
/Documentation/devicetree/bindings/clock/
Dqcom,sm8550-tcsr.yaml4 $id: http://devicetree.org/schemas/clock/qcom,sm8550-tcsr.yaml#
7 title: Qualcomm TCSR Clock Controller on SM8550
13 Qualcomm TCSR clock control module provides the clocks, resets and
17 - include/dt-bindings/clock/qcom,sm8550-tcsr.h
18 - include/dt-bindings/clock/qcom,sm8650-tcsr.h
24 - qcom,sm8550-tcsr
25 - qcom,sm8650-tcsr
26 - qcom,x1e80100-tcsr
53 compatible = "qcom,sm8550-tcsr", "syscon";
/Documentation/devicetree/bindings/phy/
Dqcom,msm8998-qmp-usb3-phy.yaml59 qcom,tcsr-reg:
63 - description: phandle to TCSR hardware block
65 description: Clamp register present in the TCSR
90 - qcom,tcsr-reg
162 qcom,tcsr-reg = <&tcsr_regs_1 0x6b244>;
Dqcom,snps-eusb2-phy.yaml72 #include <dt-bindings/clock/qcom,sm8550-tcsr.h>
Dqcom,qusb2-phy.yaml81 qcom,tcsr-syscon:
83 Phandle to TCSR syscon register region.
Dqcom,sc8280xp-qmp-pcie-phy.yaml88 - description: phandle of TCSR syscon
287 qcom,4ln-config-sel = <&tcsr 0xa044 0>;
/Documentation/devicetree/bindings/soc/qcom/
Dqcom,gsbi.yaml57 syscon-tcsr:
60 Phandle of TCSR syscon node.Required if child uses dma.
106 syscon-tcsr = <&tcsr>;
/Documentation/devicetree/bindings/remoteproc/
Dqcom,qcs404-cdsp-pil.yaml83 Phandle reference to a syscon representing TCSR followed by the
87 - description: phandle to TCSR syscon region
158 qcom,halt-regs = <&tcsr 0x19004>;
Dqcom,sdm845-adsp-pil.yaml83 Phandle reference to a syscon representing TCSR followed by the
87 - description: phandle to TCSR syscon region
Dqcom,sc7280-wpss-pil.yaml91 Phandle reference to a syscon representing TCSR followed by the
95 - description: phandle to TCSR syscon region
Dqcom,q6v5.txt90 Definition: a phandle reference to a syscon representing TCSR followed
Dqcom,msm8916-mss-pil.yaml116 - description: phandle to TCSR syscon region
265 qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
Dqcom,sc7280-adsp-pil.yaml79 Phandle reference to a syscon representing TCSR followed by the
Dqcom,sc7280-mss-pil.yaml256 qcom,ext-regs = <&tcsr 0x10000 0x10004>, <&tcsr_mutex 0x26004 0x26008>;
Dqcom,msm8996-mss-pil.yaml117 - description: phandle to TCSR syscon region
/Documentation/devicetree/bindings/usb/
Dci-hdrc-usb2.yaml55 Phandler of TCSR node with two argument that indicate register
59 - description: phandle to TCSR node
/Documentation/arch/mips/
Dingenic-tcu.rst19 different clocks (pclk, ext, rtc), gated, and reclocked, through their TCSR register.
21 - The watchdog and OST hardware blocks also feature a TCSR register with the same
/Documentation/devicetree/bindings/pci/
Dqcom,pcie-ep.yaml54 description: Reference to a syscon representing TCSR followed by the two
60 - description: Syscon to TCSR system registers
266 qcom,perst-regs = <&tcsr 0xb258 0xb270>;
/Documentation/devicetree/bindings/firmware/
Dqcom,scm.yaml113 - description: phandle to TCSR hardware block
115 description: TCSR hardware block
/Documentation/translations/zh_CN/arch/mips/
Dingenic-tcu.rst25 - 每个TCU通道都有自己的时钟源，可以通过 TCSR 寄存器设置通道的父级时钟
/Documentation/translations/zh_TW/arch/mips/
Dingenic-tcu.rst25 - 每個TCU通道都有自己的時鐘源，可以通過 TCSR 寄存器設置通道的父級時鐘
/Documentation/devicetree/bindings/bus/
Dqcom,ssc-block-bus.yaml87 - description: Phandle reference to a syscon representing TCSR
/Documentation/devicetree/bindings/power/avs/
Dqcom,cpr.yaml133 acc-syscon = <&tcsr>;