Searched full:tlb (Results 1 – 25 of 70) sorted by relevance
123
| /Documentation/devicetree/bindings/nios2/ |
| D | nios2.txt | 23 - altr,tlb-num-ways: Specifies the number of set-associativity ways in the TLB.
24 - altr,tlb-num-entries: Specifies the number of entries in the TLB.
25 - altr,tlb-ptr-sz: Specifies size of TLB pointer.
30 - altr,fast-tlb-miss-addr: Specifies CPU fast TLB miss exception address
52 altr,tlb-num-ways = <16>;
53 altr,tlb-num-entries = <128>;
54 altr,tlb-ptr-sz = <7>;
58 altr,fast-tlb-miss-addr = <0xc7fff400>;
|
| /Documentation/arch/x86/ |
| D | tlb.rst | 4 The TLB
10 1. Flush the entire TLB with a two-instruction sequence. This is
11 a quick operation, but it causes collateral damage: TLB entries
17 damage to other TLB entries.
23 entire TLB than doing 2^48/PAGE_SIZE individual flushes.
24 2. The contents of the TLB. If the TLB is empty, then there will
28 3. The size of the TLB. The larger the TLB, the more collateral
29 damage we do with a full flush. So, the larger the TLB, the
32 4. The microarchitecture. The TLB has become a multi-level
37 especially the contents of the TLB during a given flush. The
[all …]
|
| D | pti.rst | 89 feature of the MMU allows different processes to share TLB
91 TLB misses after a context switch. The actual loss of
94 allows us to skip flushing the entire TLB when switching page
99 and kernel entries out of the TLB. The user PCID TLB flush is
115 the entire TLB. That means that each syscall, interrupt
116 or exception flushes the TLB.
117 h. INVPCID is a TLB-flushing instruction which allows flushing
118 of TLB entries for non-current PCIDs. Some systems support
120 can only be flushed from the TLB for the current PCID. When
122 single kernel address flush will require a TLB-flushing CR3
[all …]
|
| D | index.rst | 21 tlb
|
| D | sva.rst | 25 mmu_notifier() support to keep the device TLB cache and the CPU cache in
79 the device TLB in sync. For example, when a page-table entry is invalidated,
80 the IOMMU propagates the invalidation to the device TLB. This will force any
258 Device TLB support - Device requests the IOMMU to lookup an address before
270 device TLB entry that might have been cached before removing the mappings from
|
| /Documentation/core-api/ |
| D | cachetlb.rst | 2 Cache and TLB Flushing Under Linux
7 This document describes the cache/tlb flushing interfaces called
17 thinking SMP cache/tlb flushing must be so inefficient, this is in
23 First, the TLB flushing interfaces, since they are the simplest. The
24 "TLB" is abstracted under Linux as something the cpu uses to cache
27 possible for stale translations to exist in this "TLB" cache.
44 the TLB. After running, this interface must make sure that
47 there will be no entries in the TLB for 'mm'.
57 address translations from the TLB. After running, this
61 running, there will be no entries in the TLB for 'mm' for
[all …]
|
| D | dma-attributes.rst | 83 the time to try to allocate memory to in a way that gives better TLB
87 - You know that the accesses to this memory won't thrash the TLB.
92 - You know that the penalty of TLB misses while accessing the
|
| /Documentation/mm/ |
| D | mmu_notifier.rst | 8 For secondary TLB (non CPU TLB) like IOMMU TLB or device TLB (when device use
11 those secondary TLB while holding page table lock when clearing a pte/pmd:
43 DEV-thread-0 {read addrA and populate device TLB}
44 DEV-thread-2 {read addrB and populate device TLB}
89 notification to invalidate the secondary TLB, the device see the new value for
|
| D | highmem.rst | 23 VM space so that we don't have to pay the full TLB invalidation costs for
147 requires global TLB invalidation when the kmap's pool wraps and it might
172 manipulate the kernel's page tables, the data TLB and/or the MMU's registers.
198 data has to be accessed to traverse in TLB fills and the like. One
|
| /Documentation/arch/arm/ |
| D | interrupts.rst | 10 MMU TLB. Each MMU TLB variant is now handled completely separately -
11 we have TLB v3, TLB v4 (without write buffer), TLB v4 (with write buffer),
12 and finally TLB v4 (with write buffer, with I TLB invalidate entry).
14 allow more flexible TLB handling for the future.
|
| /Documentation/arch/loongarch/ |
| D | introduction.rst | 111 0x10 TLB Index TLBIDX
112 0x11 TLB Entry High-order Bits TLBEHI
113 0x12 TLB Entry Low-order Bits 0 TLBELO0
114 0x13 TLB Entry Low-order Bits 1 TLBELO1
140 0x88 TLB Refill Exception Entrypoint TLBRENTRY
142 0x89 TLB Refill Exception BAD (Faulting) TLBRBADV
144 0x8A TLB Refill Exception Return Address TLBRERA
145 0x8B TLB Refill Exception Saved Data TLBRSAVE
147 0x8C TLB Refill Exception Entry Low-order TLBRELO0
149 0x8D TLB Refill Exception Entry Low-order TLBRELO1
[all …]
|
| /Documentation/features/vm/TLB/ |
| D | arch-support.txt | 2 # Feature name: batch-unmap-tlb-flush
4 # description: arch supports deferral of TLB flush until multiple pages are unmapped
|
| /Documentation/devicetree/bindings/riscv/ |
| D | cpus.yaml | 167 d-tlb-sets = <1>;
168 d-tlb-size = <32>;
173 i-tlb-sets = <1>;
174 i-tlb-size = <32>;
177 tlb-split;
|
| /Documentation/translations/zh_TW/arch/arm64/ |
| D | hugetlbpage.rst | 26 不管 TLB 中支持的條目大小如何，塊映射可以減少翻譯大頁地址
34 個 TLB 條目中。
|
| /Documentation/translations/zh_CN/arch/arm64/ |
| D | hugetlbpage.rst | 23 不管 TLB 中支持的条目大小如何，块映射可以减少翻译大页地址
31 个 TLB 条目中。
|
| /Documentation/arch/powerpc/ |
| D | cpu_families.rst | 14 - Software loaded TLB (603 and e300)
15 - Selectable Software loaded TLB in addition to hash MMU (755, 7450, e600)
127 - Software loaded TLB.
167 - Software loaded TLB.
168 - e6500 adds HW loaded indirect TLB entries.
201 | e6500 (HW TLB) (Multithreaded) |
208 - Book3E, software loaded TLB + HW loaded indirect TLB entries.
|
| /Documentation/arch/arm64/ |
| D | hugetlbpage.rst | 19 block of memory. Regardless of the supported size of entries in TLB, block
28 contiguous set of entries that can be cached in a single TLB entry.
|
| /Documentation/devicetree/bindings/iommu/ |
| D | ti,omap-iommu.txt | 19 - ti,#tlb-entries : Number of entries in the translation look-aside buffer.
39 ti,#tlb-entries = <8>;
|
| D | renesas,ipmmu-vmsa.yaml | 15 connected to the IPMMU through a port called micro-TLB.
70 The number of the micro-TLB that the device is connected to.
|
| D | qcom,tbu.yaml | 14 a Translation Lookaside Buffer (TLB) that caches page tables. TBUs provides
|
| /Documentation/admin-guide/mm/ |
| D | concepts.rst | 71 TLB). Usually TLB is pretty scarce resource and applications with
73 TLB misses.
79 `huge`. Usage of huge pages significantly reduces pressure on TLB,
80 improves TLB hit-rate and thus improves overall system performance.
|
| D | transhuge.rst | 36 1) the TLB miss will run faster (especially with virtualization using
40 2) a single TLB entry will be mapping a much larger amount of virtual
41 memory in turn reducing the number of TLB misses. With
42 virtualization and nested pagetables the TLB can be mapped of
45 the two is using hugepages just because of the fact the TLB miss is
58 architectures also employ TLB compression mechanisms to squeeze more
60 and approporiately aligned. In this case, TLB misses will occur less
|
| /Documentation/translations/zh_CN/core-api/ |
| D | cachetlb.rst | 22 *译注：TLB，Translation Lookaside Buffer，页表缓存/变换旁查缓冲器*
36 表发生变化，这个“TLB”缓存中就有可能出现过时（脏）的翻译。因此，当软件页表
76 “vma->vm_mm”的页表修改对cpu来说是可见的。也就是说，在运行后，TLB
|
| /Documentation/virt/kvm/x86/ |
| D | mmu.rst | 17 a particular implementation such as tlb size)
260 translation. This is equivalent to the state of the tlb when a pte is
261 changed but before the tlb entry is flushed. Accordingly, unsync ptes
262 are synchronized when the guest executes invlpg or flushes its tlb by
299 The guest uses two events to synchronize its tlb and page tables: tlb flushes
302 A tlb flush means that we need to synchronize all sptes reachable from the
316 pages on a tlb flush.
|
| /Documentation/admin-guide/hw-vuln/ |
| D | multihit.rst | 6 instruction fetch hits multiple entries in the instruction TLB. This can
47 processors include a structure, called TLB, that caches recent translations.
115 If EPT is disabled or not available on the host, KVM is in control of TLB
|
123