Searched full:tm (Results 1 – 25 of 38) sorted by relevance
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| /Documentation/gpu/amdgpu/ |
| D | dgpu-asic-info-table.csv | 2 AMD Radeon (TM) HD 8500M/ 8600M /M200 /M320 /M330 /M335 Series, HAINAN, --, 6, --, --
4 AMD Radeon R7 (TM|HD) M265 /M370 /8500M /8600 /8700 /8700M, OLAND, DCE 6, 6, VCE 1 / UVD 3, --
5 AMD Radeon (TM) (HD|R7) 7800 /7970 /8800 /8970 /370/ Series, PITCAIRN, DCE 6, 6, VCE 1 / UVD 3, --
6 AMD Radeon (TM|R7|R9|HD) E8860 /M360 /7700 /7800 /8800 /9000(M) /W4100 Series, VERDE, DCE 6, 6, VCE…
8 AMD Radeon (R9|TM) 200 /390 /W8100 /W9100 Series, HAWAII, DCE 8, 7, VCE 2 / UVD 4.2, 1
9 AMD Radeon (TM) R(5|7) M315 /M340 /M360, TOPAZ, *, 8, --, 2
10 AMD Radeon (TM) R9 200 /380 /W7100 /S7150 /M390 /M395 Series, TONGA, DCE 10, 8, VCE 3 / UVD 5, 3
11 AMD Radeon (FirePro) (TM) R9 Fury Series, FIJI, DCE 10, 8, VCE 3 / UVD 6, 3
12 Radeon RX 470 /480 /570 /580 /590 Series - AMD Radeon (TM) (Pro WX) 5100 /E9390 /E9560 /E9565 /V735…
13 Radeon (TM) (RX|Pro WX) E9260 /460 /V5300X /550 /560(X) Series, POLARIS11, DCE 11.2, 8, VCE 3.4 / U…
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| /Documentation/arch/powerpc/ |
| D | transactional_memory.rst | 157 suspend, we are in trouble because if we get a tm abort, the program counter and
163 state. This ensures that the signal context (written tm suspended) will be
168 For signals taken in non-TM or suspended mode, we use the
198 GDB and ptrace are not currently TM-aware. If one stops during a transaction,
202 inaccessible. GDB can currently be used on programs using TM, but not sensibly
208 TM on POWER9 has issues with storing the complete register state. This
216 To account for this different POWER9 chips have TM enabled in
219 On POWER9N DD2.01 and below, TM is disabled. ie
222 On POWER9N DD2.1 TM is configured by firmware to always abort a
223 transaction when tm suspend occurs. So tsuspend will cause a
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| /Documentation/devicetree/bindings/thermal/ |
| D | qcom-spmi-adc-tm-hc.yaml | 4 $id: http://devicetree.org/schemas/thermal/qcom-spmi-adc-tm-hc.yaml#
15 const: qcom,spmi-adc-tm-hc
61 description: Specify the sensor channel. There are 8 channels in PMIC5's ADC TM
133 adc-tm@3400 {
134 compatible = "qcom,spmi-adc-tm-hc";
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| D | thermal-sensor.yaml | 57 reg = <0 0x0c263000 0 0x1ff>, /* TM */
68 reg = <0 0x0c265000 0 0x1ff>, /* TM */
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| D | qcom-spmi-adc-tm5.yaml | 66 description: Specify the sensor channel. There are 8 channels in PMIC5's ADC TM
189 adc-tm@3500 {
238 adc-tm@3400 {
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| D | qcom-tsens.yaml | 86 - description: TM registers
317 reg = <0x4a9000 0x1000>, /* TM */
347 reg = <0x4a9000 0x1000>, /* TM */
365 reg = <0x004a9000 0x1000>, /* TM */
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| D | thermal-zones.yaml | 254 reg = <0 0x0c263000 0 0x1ff>, /* TM */
265 reg = <0 0x0c265000 0 0x1ff>, /* TM */
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| /Documentation/power/ |
| D | video.rst | 96 Acer TM 230 s3_bios (2)
97 Acer TM 242FX vbetool (6)
98 Acer TM C110 video_post (8)
99 Acer TM C300 vga=normal (only suspend on console, not in X),
101 Acer TM 4052LCi s3_bios (2)
102 Acer TM 636Lci s3_bios,s3_mode (4)
103 Acer TM 650 (Radeon M7) vga=normal plus boot-radeon (5) gets text
105 Acer TM 660 ??? [#f1]_
106 Acer TM 800 vga=normal, X patches, see webpage (5)
108 Acer TM 803 vga=normal, X patches, see webpage (5)
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| /Documentation/fb/ |
| D | modedb.rst | 39 VESA(TM) Coordinated Video Timings instead of looking up the mode from a table.
85 What is the VESA(TM) Coordinated Video Timings (CVT)?
88 From the VESA(TM) Website:
98 This is the third standard approved by VESA(TM) concerning video timings. The
100 pre-defined modes approved by VESA(TM). The second is the Generalized Timing
134 Note: VESA(TM) has restrictions on what is a standard CVT timing:
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| /Documentation/devicetree/bindings/mfd/ |
| D | qcom,spmi-pmic.yaml | 132 "^adc-tm@[0-9a-f]+$":
223 "^adc-tm@[0-9a-f]+$":
224 $ref: /schemas/thermal/qcom-spmi-adc-tm-hc.yaml#
227 "^adc-tm@[0-9a-f]+$":
330 adc-tm@3500 {
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| /Documentation/driver-api/mei/ |
| D | iamt.rst | 63 Under "SDK Resources" => "Intel(R) vPro(TM) Gateway (MPS)"
64 => "Information for Intel(R) vPro(TM) Gateway Developers"
|
| /Documentation/devicetree/bindings/ptp/ |
| D | ptp-idtcm.yaml | 7 title: IDT ClockMatrix (TM) PTP Clock
|
| /Documentation/translations/zh_CN/cpu-freq/ |
| D | index.rst | 14 Linux CPUFreq - Linux(TM)内核中的CPU频率和电压升降代码
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| /Documentation/translations/zh_TW/cpu-freq/ |
| D | index.rst | 14 Linux CPUFreq - Linux(TM)內核中的CPU頻率和電壓升降代碼
|
| /Documentation/netlink/specs/ |
| D | tc.yaml | 1510 name: tm
1544 name: tm
1557 name: tm
1570 name: tm
1632 name: tm
1663 name: tm
1700 name: tm
1722 name: tm
1738 name: tm
1771 name: tm
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| /Documentation/cpu-freq/ |
| D | index.rst | 4 CPUFreq - CPU frequency and voltage scaling code in the Linux(TM) kernel
|
| /Documentation/devicetree/bindings/power/supply/ |
| D | ltc4162-l.yaml | 15 battery charger and PowerPath (TM) manager that seamlessly manages power
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | qcom,ipq4019-pinctrl.yaml | 73 smart2, smart3, tm, wifi0, wifi1 ]
|
| /Documentation/admin-guide/ |
| D | mono.rst | 1 Mono(tm) Binary Kernel Support for Linux
|
| /Documentation/hwmon/ |
| D | fam15h_power.rst | 63 measurement interval Tm. The feature of accumulated power mechanism is
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| /Documentation/devicetree/bindings/dma/ |
| D | renesas,rz-dmac.yaml | 73 bit[15] - Specifies Transfer Mode (TM)
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| /Documentation/driver-api/ |
| D | zorro.rst | 13 AutoConfig(tm), it's 100% Plug-and-Play.
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| /Documentation/devicetree/bindings/sound/ |
| D | renesas,rz-ssi.yaml | 77 bit[15] - TM = 0, Single transfer mode
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| /Documentation/timers/ |
| D | timers-howto.rst | 6 RightWay (TM) to insert a delay?"
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| /Documentation/misc-devices/ |
| D | xilinx_sdfec.rst | 10 This driver supports SD-FEC Integrated Block for Zynq |Ultrascale+ (TM)| RFSoCs.
12 .. |Ultrascale+ (TM)| unicode:: Ultrascale+ U+2122
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