Searched full:tmr (Results 1 – 10 of 10) sorted by relevance
| /Documentation/devicetree/bindings/misc/ |
| D | xlnx,tmr-manager.yaml | 4 $id: http://devicetree.org/schemas/misc/xlnx,tmr-manager.yaml#
7 title: Xilinx Triple Modular Redundancy(TMR) Manager IP
13 The Triple Modular Redundancy(TMR) Manager is responsible for handling the
14 TMR subsystem state, including fault detection and error recovery. The core
15 is triplicated in each of the sub-blocks in the TMR subsystem, and provides
21 - xlnx,tmr-manager-1.0
43 tmr-manager@44a10000 {
44 compatible = "xlnx,tmr-manager-1.0";
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| D | xlnx,tmr-inject.yaml | 4 $id: http://devicetree.org/schemas/misc/xlnx,tmr-inject.yaml#
7 title: Xilinx Triple Modular Redundancy(TMR) Inject IP
13 The Triple Modular Redundancy(TMR) Inject core provides functional fault
15 possibility to verify that the TMR subsystem error detection and fault
21 - xlnx,tmr-inject-1.0
44 compatible = "xlnx,tmr-inject-1.0";
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| /Documentation/devicetree/bindings/ptp/ |
| D | fsl,ptp.yaml | 59 fsl,tmr-prsc:
63 fsl,tmr-add:
67 fsl,tmr-fiper1:
71 fsl,tmr-fiper2:
75 fsl,tmr-fiper3:
151 fsl,tmr-prsc = <100>;
152 fsl,tmr-add = <0x999999a4>;
153 fsl,tmr-fiper1 = <0x3b9ac9f6>;
154 fsl,tmr-fiper2 = <0x00018696>;
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| /Documentation/devicetree/bindings/timer/ |
| D | nvidia,tegra186-timer.yaml | 15 reference generated by USEC, TSC or either clk_m or OSC. Each TMR can be
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| D | nvidia,tegra-timer.yaml | 71 (TMR10-TMR13). Each TMR can be programmed to generate one-shot, periodic,
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| /Documentation/devicetree/bindings/soc/mediatek/ |
| D | mediatek,pwrap.yaml | 87 - const: tmr
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| /Documentation/netlink/specs/ |
| D | ethtool.yaml | 1077 name: to-tmr
1083 name: burst-tmr
1841 - to-tmr
1843 - burst-tmr
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| /Documentation/arch/parisc/ |
| D | registers.rst | 22 CR16 (Interval Timer) read for cycle count/write starts Interval Tmr
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| /Documentation/trace/ |
| D | timerlat-tracer.rst | 127 [tmr irq] [dev irq]
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| /Documentation/RCU/ |
| D | listRCU.rst | 446 hrtimer_cancel(&ctx->t.tmr);
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